LCMXO256E-5MN100C Lattice, LCMXO256E-5MN100C Datasheet - Page 38

• Manufacturer Part Number: LCMXO256E-5MN100C
• Description: CPLD - Complex Programmable Logic Devices 256 LUTs 78 IO 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LCMXO256E-5MN100C

• Rohs: yes
• Memory Type: SRAM
• Number Of Macrocells: 128
• Maximum Operating Frequency: 600 MHz
• Delay Time: 3.5 ns
• Number Of Programmable I/os: 78
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Package / Case: CSBGA-100
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 1800
• Supply Current: 10 mA
• Supply Voltage - Max: 1.26 V
• Supply Voltage - Min: 1.14 V

Lattice Semiconductor
Typical Building Block Function Performance
Pin-to-Pin Performance (LVCMOS25 12mA Drive)
Register-to-Register Performance
Derating Logic Timing
Logic Timing provided in the following sections of the data sheet and the ispLEVER design tools are worst case
numbers in the operating range. Actual delays may be much faster. The ispLEVER design tool from Lattice can
provide logic timing numbers at a particular temperature and voltage.
Basic Functions
16-bit decoder
4:1 MUX
16:1 MUX
Basic Functions
16:1 MUX
16-bit adder
16-bit counter
64-bit counter
Embedded Memory Functions (1200 and 2280 Devices Only)
256x36 Single Port RAM
512x18 True-Dual Port RAM
Distributed Memory Functions
16x2 Single Port RAM
64x2 Single Port RAM
128x4 Single Port RAM
32x2 Pseudo-Dual Port RAM
64x4 Pseudo-Dual Port RAM
1. The above timing numbers are generated using the ispLEVER design tool. Exact performance may vary with device and
Rev. A 0.19
tool version. The tool uses internal parameters that have been characterized but are not tested on every device.
Function
Function
-5 Timing
-5 Timing
3-12
487
292
388
200
284
284
434
320
261
314
271
6.7
4.5
5.1
1
DC and Switching Characteristics
MachXO Family Data Sheet
Units
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns