LCMXO640E-5TN144C Lattice, LCMXO640E-5TN144C Datasheet - Page 6

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LCMXO640E-5TN144C

Manufacturer Part Number
LCMXO640E-5TN144C
Description
CPLD - Complex Programmable Logic Devices 640 LUTs 113 IO 1.2V -5 Spd
Manufacturer
Lattice
Datasheet

Specifications of LCMXO640E-5TN144C

Rohs
yes
Memory Type
SRAM
Number Of Macrocells
320
Maximum Operating Frequency
600 MHz
Delay Time
3.5 ns
Number Of Programmable I/os
113
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-144
Mounting Style
SMD/SMT
Factory Pack Quantity
300
Supply Current
14 mA
Supply Voltage - Max
1.26 V
Supply Voltage - Min
1.14 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LCMXO640E-5TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Figure 2-3. Top View of the MachXO256 Device
PFU Blocks
The core of the MachXO devices consists of PFU and PFF blocks. The PFUs can be programmed to perform
Logic, Arithmetic, Distributed RAM, and Distributed ROM functions. PFF blocks can be programmed to perform
Logic, Arithmetic, and Distributed ROM functions. Except where necessary, the remainder of this data sheet will
use the term PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected Slices, numbered 0-3 as shown in Figure 2-4. There are 53 inputs
and 25 outputs associated with each PFU block.
Figure 2-4. PFU Diagram
Slice
Each Slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and
some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7, and
LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock
select, chip-select, and wider RAM/ROM functions. Figure 2-5 shows an overview of the internal logic of the Slice.
The registers in the Slice can be configured for positive/negative and edge/level clocks.
FCIN
Latch
FF/
LUT4 &
CARRY
D
Programmable
Function
Units with
RAM (PFUs)
Slice 0
JTAG Port
Latch
FF/
CARRY
LUT4 &
D
Latch
FF/
LUT4 &
CARRY
D
Slice 1
Latch
FF/
CARRY
LUT4 &
D
Routing
Routing
2-3
From
To
Latch
FF/
CARRY
LUT4 &
D
Slice 2
Programmable Function
Units without RAM (PFFs)
PIOs Arranged
into sysIO Banks
Latch
FF/
CARRY
LUT4 &
D
MachXO Family Data Sheet
Latch
FF/
CARRY
LUT4 &
D
Slice 3
Latch
FF/
CARRY
LUT4 &
D
FCO
Architecture

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