LCMXO640E-5MN100C Lattice, LCMXO640E-5MN100C Datasheet - Page 40

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LCMXO640E-5MN100C

Manufacturer Part Number
LCMXO640E-5MN100C
Description
CPLD - Complex Programmable Logic Devices 640 LUTs 74 IO 1.2V -5 Spd
Manufacturer
Lattice
Datasheet

Specifications of LCMXO640E-5MN100C

Rohs
yes
Memory Type
SRAM
Number Of Macrocells
320
Maximum Operating Frequency
600 MHz
Delay Time
3.5 ns
Number Of Programmable I/os
74
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Package / Case
CSBGA-100
Mounting Style
SMD/SMT
Factory Pack Quantity
1800
Supply Current
14 mA
Supply Voltage - Max
1.26 V
Supply Voltage - Min
1.14 V
Lattice Semiconductor
MachXO Internal Timing Parameters
PFU/PFF Logic Mode Timing
t
t
t
t
t
t
t
t
t
t
PFU Dual Port Memory Mode Timing
t
t
t
t
t
t
t
PIO Input/Output Buffer Timing
t
t
EBR Timing (1200 and 2280 Devices Only)
t
t
t
t
t
t
t
t
t
t
t
PLL Parameters (1200 and 2280 Devices Only)
t
t
1. Internal parameters are characterized but not tested on every device.
Rev. A 0.19
LUT4_PFU
LUT6_PFU
LSR_PFU
SUM_PFU
HM_PFU
SUD_PFU
HD_PFU
CK2Q_PFU
LE2Q_PFU
LD2Q_PFU
CORAM_PFU
SUDATA_PFU
HDATA_PFU
SUADDR_PFU
HADDR_PFU
SUWREN_PFU
HWREN_PFU
IN_PIO
OUT_PIO
CO_EBR
COO_EBR
SUDATA_EBR
HDATA_EBR
SUADDR_EBR
HADDR_EBR
SUWREN_EBR
HWREN_EBR
SUCE_EBR
HCE_EBR
RSTO_EBR
RSTREC
RSTSU
Parameter
LUT4 delay (A to D inputs to F output)
LUT6 delay (A to D inputs to OFX output)
Set/Reset to output of PFU
Clock to Mux (M0,M1) input setup time
Clock to Mux (M0,M1) input hold time
Clock to D input setup time
Clock to D input hold time
Clock to Q delay, D-type register configuration
Clock to Q delay latch configuration
D to Q throughput delay when latch is enabled
Clock to Output
Data Setup Time
Data Hold Time
Address Setup Time
Address Hold Time
Write/Read Enable Setup Time
Write/Read Enable Hold Time
Input Buffer Delay
Output Buffer Delay
Clock to output from Address or Data with no output
register
Clock to output from EBR output Register
Setup Data to EBR Memory
Hold Data to EBR Memory
Setup Address to EBR Memory
Hold Address to EBR Memory
Setup Write/Read Enable to EBR Memory
Hold Write/Read Enable to EBR Memory
Clock Enable Setup Time to EBR Output Register
Clock Enable Hold Time to EBR Output Register
Reset To Output Delay Time from EBR Output Regis-
ter
Reset Recovery to Rising Clock
Reset Signal Setup Time
Description
Over Recommended Operating Conditions
1
3-14
-0.05
-0.03
-0.18
-0.46
-0.22
-0.26
-0.26
-0.17
-0.13
Min.
0.10
0.28
0.71
0.33
0.41
1.00
0.13
0.41
0.26
0.19
1.00
-5
DC and Switching Characteristics
Max.
0.28
0.44
0.90
0.40
0.53
0.55
0.40
0.75
1.29
2.24
0.54
1.03
-0.06
-0.03
-0.22
-0.56
-0.26
-0.31
-0.31
-0.20
-0.16
MachXO Family Data Sheet
Min.
0.13
0.16
0.34
0.85
0.40
0.49
0.49
0.31
0.23
1.00
1.00
-4
Max.
0.34
0.53
1.08
0.48
0.64
0.66
0.48
0.90
1.54
2.69
0.64
1.23
-0.04
-0.25
-0.30
-0.37
-0.18
-0.07
-0.65
-0.37
-0.23
Min.
0.15
0.18
0.39
0.99
0.47
0.57
0.57
0.36
0.27
1.00
1.00
-3
Max.
0.39
0.62
1.26
0.56
0.74
0.77
0.56
1.06
1.80
3.14
0.75
1.44
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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