LCMXO1200E-5TN100C Lattice, LCMXO1200E-5TN100C Datasheet - Page 3

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LCMXO1200E-5TN100C

Manufacturer Part Number
LCMXO1200E-5TN100C
Description
CPLD - Complex Programmable Logic Devices 1200 LUTs 73 IO 1.2V -5 Spd
Manufacturer
Lattice
Datasheet

Specifications of LCMXO1200E-5TN100C

Rohs
yes
Memory Type
SRAM
Number Of Macrocells
600
Maximum Operating Frequency
600 MHz
Delay Time
3.6 ns
Number Of Programmable I/os
73
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-100
Mounting Style
SMD/SMT
Factory Pack Quantity
450
Supply Current
18 mA
Supply Voltage - Max
1.26 V
Supply Voltage - Min
1.14 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LCMXO1200E-5TN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Introduction
Lattice Semiconductor
MachXO Family Data Sheet
The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flex-
ible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, high-
security, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and
careful design will provide the high pin-to-pin performance also associated with CPLDs.
®
The ispLEVER
design tools from Lattice allow complex designs to be efficiently implemented using the MachXO
family of devices. Popular logic synthesis tools provide synthesis library support for MachXO. The ispLEVER tools
use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in
the MachXO device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design
for timing verification.
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