LCMXO1200E-5TN100C Lattice, LCMXO1200E-5TN100C Datasheet - Page 96

• Manufacturer Part Number: LCMXO1200E-5TN100C
• Description: CPLD - Complex Programmable Logic Devices 1200 LUTs 73 IO 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LCMXO1200E-5TN100C

• Rohs: yes
• Memory Type: SRAM
• Number Of Macrocells: 600
• Maximum Operating Frequency: 600 MHz
• Delay Time: 3.6 ns
• Number Of Programmable I/os: 73
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-100
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 450
• Supply Current: 18 mA
• Supply Voltage - Max: 1.26 V
• Supply Voltage - Min: 1.14 V

Lattice Semiconductor
November 2006
December 2006
November 2007
February 2007
August 2007
June 2009
July 2010
Date
Version
02.3
02.4
02.5
02.6
02.7
02.8
02.9
Ordering Information
Pinout Information
Pinout Information
Pinout Information
DC and Switching
DC and Switching
DC and Switching
DC and Switching
Characteristics
Characteristics
Characteristics
Characteristics
Supplemental
Architecture
Architecture
Introduction
Information
Section
Corrections to MachXO “C” Sleep Mode Timing table - value for
t
(100ns) changed from min. to max.
Added Flash Download Time table.
EBR Asynchronous Reset section added.
Power Supply and NC table: Pin/Ball orientation footnotes added.
Updated EBR Asynchronous Reset section.
Updated sysIO Single-Ended DC Electrical Characteristics table.
Added JTAG Port Timing Waveforms diagram.
Added Thermal Management text section.
Updated title list.
Added 0.8-mm 256-pin caBGA package to MachXO Family Selection
Guide table.
Added Logic Signal Connections table for 0.8-mm 256-pin caBGA pack-
age.
Updated Part Number Description diagram and Ordering Part Number
tables with 0.8-mm 256-pin caBGA package information.
Updated sysCLOCK PLL Timing table.
WSLEEPN
7-3
(400ns) changed from max. to min. Value for t
Change Summary
MachXO Family Data Sheet
Revision History
WAWAKE