LCMXO640E-5FN256C Lattice, LCMXO640E-5FN256C Datasheet - Page 42

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LCMXO640E-5FN256C

Manufacturer Part Number
LCMXO640E-5FN256C
Description
CPLD - Complex Programmable Logic Devices Use LCMXO640E-5FTN25
Manufacturer
Lattice
Datasheet

Specifications of LCMXO640E-5FN256C

Rohs
yes
Memory Type
SRAM
Number Of Macrocells
320
Maximum Operating Frequency
600 MHz
Delay Time
3.5 ns
Number Of Programmable I/os
159
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Package / Case
FPBGA
Mounting Style
SMD/SMT
Factory Pack Quantity
450
Supply Current
14 mA
Supply Voltage - Max
1.26 V
Supply Voltage - Min
1.14 V
Lattice Semiconductor
sysCLOCK PLL Timing
MachXO “C” Sleep Mode Timing
t
t
t
t
Rev. A 0.19
PWRDN
PWRUP
WSLEEPN
WAWAKE
f
f
f
f
f
AC Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
1. Jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock.
2. Output clock is valid after t
3. Using LVDS output buffers.
4. CLKOS as compared to CLKOP output.
5. When using an input frequency less than 25 MHz the output frequency must be less than or equal to 4 times the input frequency.
6. The on-chip oscillator can be used to provide reference clock input to the PLL provided the output frequency restriction for clock
Rev. A 0.19
Symbol
IN
OUT
OUT2
VCO
PFD
DT
PH
OPJIT
SK
W
LOCK
PA
IPJIT
FBKDLY
HI
LO
RST
Parameter
inputs below 25 MHz are followed.
4
2
1
Input Clock Frequency (CLKI, CLKFB)
Output Clock Frequency (CLKOP, CLKOS)
K-Divider Output Frequency (CLKOK)
PLL VCO Frequency
Phase Detector Input Frequency
Output Clock Duty Cycle
Output Phase Accuracy
Output Clock Period Jitter
Input Clock to Output Clock Skew
Output Clock Pulse Width
PLL Lock-in Time
Programmable Delay Unit
Input Clock Period Jitter
External Feedback Delay
Input Clock High Time
Input Clock Low Time
RST Pulse Width
SLEEPN Low to Power Down
SLEEPN High to Power Up
SLEEPN Pulse Width
SLEEPN Pulse Rejection
LOCK
Descriptions
Parameter
for PLL reset and dynamic delay adjustment.
Over Recommended Operating Conditions
3-16
Input Divider (M) = 1;
Feedback Divider (N) <= 4
Input Divider (M) = 1; 
Feedback Divider (N) <= 4
Default duty cycle selected
f
f
Divider ratio = integer
At 90% or 10%
f
f
90% to 90%
10% to 10%
All
LCMXO256
LCMXO640
LCMXO1200
LCMXO2280
All
All
OUT
OUT
OUT
OUT
>= 100 MHz
< 100 MHz
 100 MHz
< 100 MHz
Device
Conditions
DC and Switching Characteristics
3
MachXO Family Data Sheet
Min.
400
5, 6
5, 6
3
0.195
Min.
420
100
0.5
0.5
25
18
25
25
18
45
10
1
Typ.
+/-120
+/-200
+/-200
Max.
0.05
0.02
0.02
420
420
210
840
150
450
25
25
55
10
1000
Max
400
400
600
800
100
Units
UIPP
MHz
MHz
MHz
MHz
MHz
MHz
MHz
UI
ps
ps
ns
µs
ps
ps
UI
ns
ns
ns
ns
%
Units
ns
µs
µs
µs
µs
ns
ns

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