NB7VPQ16MMNG ON Semiconductor, NB7VPQ16MMNG Datasheet

IC CML PRE-EMPH DRIVER 16QFN

NB7VPQ16MMNG

Manufacturer Part Number
NB7VPQ16MMNG
Description
IC CML PRE-EMPH DRIVER 16QFN
Manufacturer
ON Semiconductor
Datasheet

Specifications of NB7VPQ16MMNG

Logic Type
CML Driver with Selectable Equalizer Receiver
Supply Voltage
1.71 V ~ 2.625 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Bits
-
Lead Free Status / Rohs Status
Compliant

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Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
NB7VPQ16MMNG
Manufacturer:
ON Semiconductor
Quantity:
105
Price:
NB7VPQ16M
1.8V/2.5V CML 12.5 Gbps
Programmable Pre-Emphasis
Copper/Cable Driver with
Selectable Equalizer Receiver
Multi−Level Inputs w/ Internal Termination
Description
programmable Pre−Emphasis CML Driver with a selectable Equalizer
Receiver that operates up to 14 Gbps typical with a 1.8 V or 2.5 V
power supply. When placed in series with a Data/Clock path, the
NB7VPQ16M inputs will compensate the degraded signal transmitted
across a FR4 PCB backplane or cable interconnect. Therefore, the
serial data rate is increased by reducing Inter−Symbol Interference
(ISI) caused by losses in copper interconnect or long cables.
Serial Data In (SDIN) and Serial Clock In (SCLKIN) control inputs
and contains circuitry which provides sixteen programmable
Pre−Emphasis settings to select the optimal output compensation
level.
and cable lines. The first four SDIN bits (D3:D0) will digitally select
0 dB through 12 dB typical of de−emphasis (see Table 1).
are presented at the SDOUT and SCLKOUT pins.
equalization function of the receiver.
50 W termination resistors, in a 100 W center−tapped configuration,
via the VT pin and will accept LVPECL, CML or LVDS logic levels.
This feature provides transmission line termination on−chip, at the
receiver end, eliminating external components.
performance Data/Clock products with Pre−Emphasis/Equalization
(PEEQ).
Features
© Semiconductor Components Industries, LLC, 2009
July, 2009 − Rev. 0
The NB7VPQ16M is a high performance single channel
The Pre−Emphasis buffer is controlled using a serial bus via the
These selectable output levels will handle various backplane lengths
For cascaded applications, the shifted SDIN and SCLKIN signals
The 5
The differential Data / Clock inputs incorporate a pair of internal
The NB7VPQ16M is a member of the GigaComm™ Family of high
Maximum Input Data Rate > 12.5 Gbps
Maximum Input Clock Frequency > 8 GHz
Drives Up To 18−inches of FR4
(16) Programmable Output De−emphasis Levels; 0 dB
through 12 dB
200 ps Typical Propagation Delay
Differential CML Outputs, 400 mV Peak−to−Peak,
Typical (PE = 0 dB)
th
−bit (LSB) of the serial data bits allows for enabling the
1
Operating Range: V
Internal Output Termination Resistors, 50 W
QFN−16 Package, 3 mm x 3 mm
−40°C to +85°C Ambient Operating Temperature
These are Pb−Free Devices
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
VT
*For additional marking information, refer to
CASE 485G
MN SUFFIX
(Note: Microdot may be in either location)
Application Note AND8002/D.
Figure 1. Simplified Logic Diagram
IN
IN
QFN−16
1
ORDERING INFORMATION
A
L
Y
W
G
CC
http://onsemi.com
= 1.71 V to 2.625 V, GND = 0 V
EQ
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
SLOAD
SCLKIN
SDIN
Publication Order Number:
1
16
DIAGRAM*
MARKING
PQ16M
ALYWG
DAC
NB7V
SDI
PE
G
NB7VPQ16M/D
SDOUT
SCLKOUT
Q
Q

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NB7VPQ16MMNG Summary of contents

Page 1

NB7VPQ16M 1.8V/2.5V CML 12.5 Gbps Programmable Pre-Emphasis Copper/Cable Driver with Selectable Equalizer Receiver Multi−Level Inputs w/ Internal Termination Description The NB7VPQ16M is a high performance single channel programmable Pre−Emphasis CML Driver with a selectable Equalizer Receiver that operates up to ...

Page 2

Multi−Level Inputs LVPECL, LVDS, CML (2) IN 50W (1) VT 50W (3) IN Figure 2. Detailed Block Diagram of NB7VPQ16M Q Low Q High Bit n − OD0dB V ODPE Figure 3. Illustration of Output Waveform ...

Page 3

Table 1. TYPICAL PRE−EMPHASIS CONTROL TABLE 255C, V MSB D3 Decimal ...

Page 4

Table 3. PIN DESCRIPTION Pin Name I LVPECL, CML, LVDS Input 3 IN LVPECL, CML, LVDS Input 4 GND − 5 VCCD − 6 SDOUT LVCMOS Output 7 SCLKOUT LVCMOS Output 8 GND − 9 VCC ...

Page 5

Table 4. ATTRIBUTES ESD Protection Internal Input Pulldown Resistor Moisture Sensitivity, Indefinite Time Out of Drypack (Note 3) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table ...

Page 6

Table 6. DC CHARACTERISTICS POSITIVE CML OUTPUT (Note 5) Symbol POWER SUPPLY CURRENT I Power Supply Current, (Inputs and Outputs Open 0dB I Power Supply Current for Serial Bus and DAC CCD (Inputs and Outputs Open) CML ...

Page 7

Table 7. AC CHARACTERISTICS V Symbol f Maximum Input Data Rate DATAMAX f Maximum Input Clock Frequency (Note 9) MAX f Serial Clock Input Frequency SCLKIN VOD Output Voltage Amplitude (see Table 1) 0dB (@ V ) (See Figure 3, ...

Page 8

IHD(IN IHD IN V ILD Figure 6. Differential Inputs Driven Differentially CMmax V CMR V CMmin GND SDIN SCLKIN Figure 9. SDIN/SCLKIN Setup and Hold Time IN ...

Page 9

Data Inputs The differential IN/IN inputs of the NB7VPQ16M can accept LVPECL, CML, and LVDS signal levels. The limitations for a differential input signal (LVDS, LVPECL, or CML minimum input swing of 100 mV (single−ended measurement). Within this ...

Page 10

SDOUT/SCLKOUT SDOUT is the Serial Data output pin; SCLKOUT is the Serial Clock output pin. These pins are the outputs of the 5−bit SDI shift register and will produce the SDIN/SCLKIN SDIN EQEN ...

Page 11

INA DUTA EQA SLOAD Serial Data In SDINA PEA Serial Clock In SCLKINA CML QA Figure 13. Simplified Cascaded Logic Diagram DUTC SDIN D3C D2C D1C D0C D3B EQC SCLKIN Clocks t PD SCLKIN ...

Page 12

Signal Generator Signal Generator Output 20 mV/div 28 ps/div Signal Generator Output 20 mV/div 28 ps/div Figure 15. Typical NB7VPQ16M Equalizer Application and Interconnect; Eye Diagrams with PRBS23 Pattern at NB7VPQ16M Equalizer Receiver and 1 FR4 = ...

Page 13

NB7VPQ16M Pre−emphasis Driver Q Signal Generator Q Signal Generator Output 20 mV/div 28 ps/div Signal Generator Output 20 mV/div 28 ps/div Figure 16. Typical NB7VPQ16M Pre−Emphasis Application Interconnect; Eye Diagrams with PRBS23 Pattern at FR4 = 12” Backplane NB7VPQ16M Output ...

Page 14

V CC NB7VPQ16M LVPECL − Driver GND Figure 17. LVPECL Interface CML V = ...

Page 15

... Driver Device Figure 24. Typical Termination for CML Output Driver and Device Evaluation ORDERING INFORMATION Device NB7VPQ16MMNG NB7VPQ16MMNTXG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Receiver NB7VPQ16M ...

Page 16

... E2 e 3.25 0.128 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81− ...

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