NB7VPQ16MMNG ON Semiconductor, NB7VPQ16MMNG Datasheet - Page 9

IC CML PRE-EMPH DRIVER 16QFN

NB7VPQ16MMNG

Manufacturer Part Number
NB7VPQ16MMNG
Description
IC CML PRE-EMPH DRIVER 16QFN
Manufacturer
ON Semiconductor
Datasheet

Specifications of NB7VPQ16MMNG

Logic Type
CML Driver with Selectable Equalizer Receiver
Supply Voltage
1.71 V ~ 2.625 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Bits
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NB7VPQ16MMNG
Manufacturer:
ON Semiconductor
Quantity:
105
Data Inputs
accept LVPECL, CML, and LVDS signal levels. The
limitations for a differential input signal (LVDS, LVPECL,
or CML) is a minimum input swing of 100 mV
(single−ended measurement). Within this condition, the
input HIGH voltage, V
1.1 V. Example interfaces are illustrated in Figure 17.
Serial Data Interface
a 5−bit shift register scheme. The register shifts once per
rising edge of the SCLKIN input. The serial data input SDIN
must meet setup and hold timing as specified in the AC table.
The configuration latches will capture the value of the shift
register on the Low−to−High edge of the SLOAD input. The
most significant bit (MSB) is loaded first. See the
programming timing diagram for more information.
Pre−Emphasis Selection
via the SDIN (Serial Data In) and SCLKIN (Serial Clock In)
control inputs and contains circuitry which provides sixteen
programmable pre−emphasis levels to control the output
compensation. The 4−bits (D3:D0) digitally select 0 dB
through 12 dB of Pre−Emphasis compensation (see
Table 1). The default state at start−up is PE = 0 dB.
EQualization ENable (EQEN)
Equalizer function. The control of the Equalizer function is
realized by setting the 5th bit, EQEN, of the 5−bit serial data.
When EQEN is set Low (or open), the IN/IN inputs bypass
the Equalizer. When EQEN is set High, the IN/IN inputs
flow through the Equalizer. The default state at start−up is
EQEN = LOW.
The differential IN/IN inputs of the NB7VPQ16M can
The Serial Data Interface (SDI) logic is implemented with
The Pre−Emphasis buffer is controlled using a serial bus
The EQualizer ENable (EQEN) allows for enabling the
SLOAD
SCLKOUT
SDIN
SDOUT
SCLKIN
D3
1
IH
/////
, can range from V
1
D2
2
/////
5 Clock
2
D1
Figure 11. Timing Diagram for Single Channel
3
t
/////
PWMIN
D0
3
APPLICATION INFORMATION
4
CC
/////
down to
EQEN
4
http://onsemi.com
5
D3
5
/////
SCLKIN to SDOUT
9
6
SDIN / SCLKIN
Clock input pin.
SLOAD
LOW or left open, the DAC latch will pass the shift register
outputs to the input of the DAC and the EQualizer ENable
bit (EQEN). On the Low−to−HIGH transition of SLOAD,
the input to the 4−bit DAC is locked to the state prior to when
SLOAD went HIGH, and will set the EQualizer ENable bit.
The DAC does not get programmed until SLOAD goes
HIGH. The SLOAD pin must remain in a HIGH state to
maintain the DAC Pre−Emphasis and the EQEN settings. A
LOW or open state resets the DAC to 0 db Pre−Emphasis
setting and disables the EQEN bit, regardless of SDIN and
SCLKIN values. The SLOAD function is asynchronous.
D2
Q/Q Outputs
utilize Common Mode Logic (CML) architecture. The
outputs are designed to drive differential transmission lines
with nominal 50 W characteristic impedance. External
termination with a 50 W resistor to V
See Figures 22 and 23 for output termination scheme.
Alternatively, 100 W line−to−line termination is also
acceptable.
Power Supply Bypass information
the NB7VPQ16M. The device provides separate V
V
outputs. Placing a 0.01 mF to 0.1 mF bypass capacitor on
each V
free power supply. The purpose of this design technique is
to isolate the CMOS digital switching noise from the high
speed input/output path.
CC
SDIN is the Serial Data input pin; SCLKIN is the Serial
The SLOAD pin performs the DAC latch function. When
The differential outputs of the NB7VPQ16M, Q and Q,
A clean power supply will optimize the performance of
6
/////
7
power supply pins for the digital circuitry and CML
CC
D1
and V
/////
7
8
D0
CCD
/////
8
9
Pin to ground will help ensure a noise
EQEN
9
/////
10
/////
10
/////
11
CC
/////
is recommended.
11
/////
12
/////
CCD
and

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