C8051F964-A-GQ Silicon Labs, C8051F964-A-GQ Datasheet
C8051F964-A-GQ
Specifications of C8051F964-A-GQ
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C8051F964-A-GQ Summary of contents
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Ultra Low Power Consumption at 3.6V - 130 µA/MHz Low-Power Active mode with dc-dc enabled - 110 nA sleep current w/ data retention; POR monitor enabled 400 nA sleep mode with SmaRTClock - (internal LFO) - 700 nA sleep ...
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C8051F96x 2 Rev. 0.5 ...
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Table of Contents 1. System Overview ..................................................................................................... 23 1.1. CIP-51™ Microcontroller Core .......................................................................... 29 1.1.1. Fully 8051 Compatible .............................................................................. 29 1.1.2. Improved Throughput................................................................................ 29 1.1.3. Additional Features ................................................................................... 29 1.2. Port Input/Output ............................................................................................... 30 1.3. Serial Ports ........................................................................................................ 31 1.4. ...
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C8051F96x 5.10. External Voltage Reference........................................................................... 101 5.11. Internal Voltage Reference............................................................................ 101 5.12. Analog Ground Reference............................................................................. 101 5.13. Temperature Sensor Enable ......................................................................... 101 5.14. Voltage Reference Electrical Specifications .................................................. 102 6. Programmable Current Reference (IREF0).......................................................... 103 6.1. PWM Enhanced Mode..................................................................................... 103 ...
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DMA0 Memory Access Arbitration ........................................................ 148 11.2.2. DMA0 Channel Arbitration .................................................................... 148 11.3. DMA0 Operation in Low Power Modes ......................................................... 148 11.4. Transfer Configuration................................................................................... 149 12. Cyclic Redundancy Check Unit (CRC0)............................................................. 160 12.1. 16-bit CRC Algorithm..................................................................................... 160 12.3. Preparing ...
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C8051F96x 15. Encoder/Decoder ................................................................................................. 207 15.1. Manchester Encoding.................................................................................... 208 15.2. Manchester Decoding.................................................................................... 209 15.3. Three-out-of-Six Encoding............................................................................ 210 15.4. Three-out-of-Six Decoding ............................................................................ 211 15.5. Encoding/Decoding with SFR Access ........................................................... 212 15.6. Decoder Error Interrupt.................................................................................. 212 15.7. Using the ENC0 module with ...
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Selecting the Optimum Switch Size............................................................... 271 20.6. DC-DC Converter Clocking Options .......................................................... 271 20.7. Bypass Mode................................................................................................. 272 20.8. DC-DC Converter Register Descriptions ....................................................... 272 20.9. DC-DC Converter Specifications ................................................................... 276 21. Voltage Regulator (VREG0)................................................................................. 277 21.1. Voltage Regulator Electrical ...
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C8051F96x 24.3.2. Setting a SmaRTClock Alarm ............................................................... 305 24.3.3. Software Considerations for using the SmaRTClock Timer and Alarm 305 25. Low-Power Pulse Counter .................................................................................. 312 25.1. Counting Modes ............................................................................................ 313 25.2. Reed Switch Types........................................................................................ 314 25.3. Programmable Pull-Up Resistors .................................................................. ...
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Arbitration.............................................................................................. 383 28.3.3. Clock Low Extension............................................................................. 383 28.3.4. SCL Low Timeout.................................................................................. 383 28.3.5. SCL High (SMBus Free) Timeout ......................................................... 384 28.4. Using the SMBus........................................................................................... 384 28.4.1. SMBus Configuration Register.............................................................. 384 28.4.2. SMB0CN Control Register .................................................................... 388 28.4.3. Hardware Slave ...
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C8051F96x 32.3.3. SmaRTClock/External Oscillator Capture Mode ................................... 461 33. Programmable Counter Array............................................................................. 466 33.1. PCA Counter/Timer ....................................................................................... 467 33.2. PCA0 Interrupt Sources................................................................................. 468 33.3. Capture/Compare Modules ........................................................................... 469 33.3.1. Edge-triggered Capture Mode............................................................... 470 33.3.2. Software Timer (Compare) Mode.......................................................... 471 33.3.3. ...
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... List of Figures Figure 1.1. C8051F960 Block Diagram ................................................................... 24 Figure 1.2. C8051F961 Block Diagram ................................................................... 24 Figure 1.3. C8051F962 Block Diagram ................................................................... 25 Figure 1.4. C8051F963 Block Diagram ................................................................... 25 Figure 1.5. C8051F964 Block Diagram ................................................................... 26 Figure 1.6. C8051F965 Block Diagram ................................................................... 26 Figure 1.7. C8051F966 Block Diagram ................................................................... 27 Figure 1.8. C8051F967 Block Diagram ................................................................... 27 Figure 1.9. C8051F968 Block Diagram ................................................................... 28 Figure 1.10. C8051F969 Block Diagram ................................................................. 28 Figure 1 ...
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C8051F96x Figure 8.1. CIP-51 Block Diagram ......................................................................... 115 Figure 9.1. C8051F96x Memory Map .................................................................... 124 Figure 9.2. Flash Program Memory Map ............................................................... 125 Figure 9.3. Address Memory Map for Instruction Fetches ..................................... 126 Figure 10.1. Multiplexed Configuration Example ................................................... 134 ...
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Figure 26.5. Contrast Control Mode 3 ................................................................... 339 Figure 26.6. Contrast Control Mode 4 ................................................................... 340 Figure 27.1. Port I/O Functional Block Diagram .................................................... 351 Figure 27.2. Port I/O Cell Block Diagram .............................................................. 352 Figure 27.3. Crossbar Priority Decoder with ...
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C8051F96x Figure 33.4. PCA Capture Mode Diagram ............................................................. 471 Figure 33.5. PCA Software Timer Mode Diagram ................................................. 472 Figure 33.6. PCA High-Speed Output Mode Diagram ........................................... 473 Figure 33.7. PCA Frequency Output Mode ........................................................... 474 Figure 33.8. PCA 8-Bit PWM ...
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List of Tables Table 2.1. Product Selection Guide ......................................................................... 35 Table 3.1. Pin Definitions for the C8051F96x .......................................................... 36 Table 3.2. DQFN-76 Package Dimensions ............................................................. 46 Table 3.3. DQFN-76 Land Pattern Dimensions ....................................................... 47 Table 3.4. Recomended Inner Via Placement ...
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C8051F96x Table 15.5. Three-out-of-Six Decoding ................................................................. 211 Table 16.1. SFR Map (0xC0–0xFF) ...................................................................... 222 Table 16.2. SFR Map (0x80–0xBF) ....................................................................... 223 Table 16.3. Special Function Registers ................................................................. 224 Table 17.1. Interrupt Summary .............................................................................. 234 Table 18.1. Flash Security Summary .................................................................... ...
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List of Registers SFR Definition 5.1. ADC0CN: ADC0 Control ................................................................ 86 SFR Definition 5.2. ADC0CF: ADC0 Configuration ...................................................... 87 SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration ................................. 88 SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time ............................ 89 SFR ...
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C8051F96x SFR Definition 11.11. DMA0NAOL: Memory Address Offset Low Byte ..................... 158 SFR Definition 11.12. DMA0NSZH: Transfer Size High Byte ..................................... 159 SFR Definition 11.13. DMA0NSZL: Memory Transfer Size Low Byte ........................ 159 SFR Definition 12.1. CRC0CN: CRC0 Control ........................................................... ...
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SFR Definition 19.3. CLKMODE: Clock Mode ............................................................ 262 SFR Definition 19.4. PMU0CF: Power Management Unit Configuration SFR Definition 19.5. PMU0FL: Power Management Unit Flag SFR Definition 19.6. PMU0MD: Power Management Unit Mode ................................ 267 SFR Definition 19.7. PCON: Power Management ...
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C8051F96x SFR Definition 25.19. PC0HIST: PC0 History ............................................................ 331 SFR Definition 25.20. PC0INT0: PC0 Interrupt 0 ........................................................ 332 SFR Definition 25.21. PC0INT1: PC0 Interrupt 1 ........................................................ 333 SFR Definition 26.1. LCD0Dn: LCD0 Data ................................................................. 335 SFR Definition 26.2. LCD0CN: LCD0 ...
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SFR Definition 27.24. P3MDIN: Port3 Input Mode ...................................................... 372 SFR Definition 27.25. P3MDOUT: Port3 Output Mode ............................................... 372 SFR Definition 27.26. P3DRV: Port3 Drive Strength .................................................. 373 SFR Definition 27.27. P4: Port4 .................................................................................. 373 SFR Definition 27.28. P4MDIN: Port4 Input ...
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C8051F96x SFR Definition 32.13. TMR3CN: Timer 3 Control ....................................................... 463 SFR Definition 32.14. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 464 SFR Definition 32.15. TMR3RLH: Timer 3 Reload Register High Byte ...................... 464 SFR Definition 32.16. TMR3L: Timer 3 ...
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... The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands ...
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C8051F96x CIP-51 8051 Power On Controller Core Reset/PMU 128k Byte ISP Flash Wake Program Memory Reset 256 Byte SRAM C2CK/RST Debug / Programming 8092 Byte XRAM Hardware C2D VBAT Analog VBAT VREG Power VDD Digital VREG VDC Power VBATDC DC/DC ...
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CIP-51 8051 Power On Controller Core Reset/PMU 128k Byte ISP Flash Wake Program Memory Reset 256 Byte SRAM C2CK/RST Debug / Programming 8092 Byte XRAM Hardware C2D DMA VBAT Analog CRC VBAT VREG Power Engine VDD Digital VREG AES VDC ...
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... External XTAL1 Oscillator XTAL2 Circuit Enhanced XTAL3 GND smaRTClock Oscillator XTAL4 System Clock Configuration Figure 1.5. C8051F964 Block Diagram CIP-51 8051 Power On Controller Core Reset/PMU 64k Byte ISP Flash Wake Program Memory Reset 256 Byte SRAM Debug / C2CK/RST Programming 8092 Byte XRAM ...
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CIP-51 8051 Power On Controller Core Reset/PMU 32k Byte ISP Flash Wake Program Memory Reset 256 Byte SRAM C2CK/RST Debug / Programming 8092 Byte XRAM Hardware C2D DMA VBAT Analog CRC VBAT VREG Power Engine VDD Digital VREG AES VDC ...
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C8051F96x CIP-51 8051 Power On Controller Core Reset/PMU 16k Byte ISP Flash Wake Program Memory Reset 256 Byte SRAM C2CK/RST Debug / Programming 4096 Byte XRAM Hardware C2D VBAT Analog VBAT VREG Power VDD Digital VREG VDC Power VBATDC DC/DC ...
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... CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F96x family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052. ...
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C8051F96x 1.2. Port Input/Output Digital and analog resources are available through 57 I/O pins (C8051F960/2/4/6/ I/O pins (C8051F961/3/5/7/9). Port pins are organized as eight byte-wide ports. Port pins can be defined as digital or analog I/O. Digital I/O ...
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Serial Ports The C8051F96x Family includes an SMBus/I configuration, and two Enhanced SPI interfaces. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. 1.4. ...
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C8051F96x 1.5. SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode The ADC0 on C8051F96x devices is a 300 ksps, 10-bit or 75 ksps, 12-bit successive-approximation-regis- ter (SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 ...
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P0.0 P2.6* Temp Sensor VBAT Digital Supply VDD/DC+ *P1.7-P2. 6 only available as inputs on 32- pin packages Figure 1.14. ADC0 Multiplexer Block Diagram 1.6. Programmable Current Reference (IREF0) C8051F96x devices include an on-chip programmable current reference (source or sink) ...
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C8051F96x CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 Analog Input Multiplexer Px.x CP0 + Px.x Px.x CP0 - Px.x Figure 1.15. Comparator 0 Functional Block Diagram CP1EN CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 Analog Input Multiplexer Px.x CP1 ...
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... Table 2.1. Product Selection Guide C8051F960-A-GM 25 128 8448 57 C8051F960-A-GQ 25 128 8448 57 C8051F961-A-GM 25 128 8448 34 C8051F962-A-GM 25 128 8448 57 C8051F962-A-GQ 25 128 8448 57 C8051F963-A-GM 25 128 8448 34 C8051F964-A- 8448 57 C8051F964-A- 8448 57 C8051F965-A- 8448 34 C8051F966-A- 8448 57 C8051F966-A- 8448 57 C8051F967-A- 8448 34 C8051F968-A-GM ...
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C8051F96x 3. Pinout and Package Definitions Table 3.1. Pin Definitions for the C8051F96x Pin Numbers Name DQFN76 TQFP80 QFN40 VBAT A5 8 VBATDC A6 10 VDC A8 14 GNDDC A 12 GND B6 13,64,66 ,68 IND B5 11 VIO B4 ...
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Table 3.1. Pin Definitions for the C8051F96x (Continued) Pin Numbers Name DQFN76 TQFP80 QFN40 P0 REF P0 AGND P0 XTAL1 P0 XTAL2 P0.4 A40 79 TX P0.5 A39 78 RX P0.6 ...
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C8051F96x Table 3.1. Pin Definitions for the C8051F96x (Continued) Pin Numbers Name DQFN76 TQFP80 QFN40 P1.0 A36 72 PC0 P1.1 A35 70 PC1 P1.2 A34 67 XTAL3 P1.3 A33 65 XTAL4 P1.4 A31 60 P1.5 A30 57 P1.6 A29 56 ...
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Table 3.1. Pin Definitions for the C8051F96x (Continued) Pin Numbers Name DQFN76 TQFP80 QFN40 P2.6 A21 43 21 COM2 P2.7 A20 41 20 COM2 P3.0 A19 39 19 LCD0 P3.1 A18 38 18 LCD1 P3.2 A17 36 17 LCD2 P3.3 ...
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C8051F96x Table 3.1. Pin Definitions for the C8051F96x (Continued) Pin Numbers Name DQFN76 TQFP80 QFN40 P4.0 A11 23 LCD8 P4 LCD9 P4 LCD10 P4 LCD11 P4 LCD12 P4.5 B28 77 LCD13 P4.6 ...
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Table 3.1. Pin Definitions for the C8051F96x (Continued) Pin Numbers Name DQFN76 TQFP80 QFN40 P5.2 B23 63 LCD18 P5.3 B22 62 LCD19 P5 LCD20 P5.5 B21 55 LCD21 P5.6 B15 44 LCD22 P5 LCD23 P6.0 B14 ...
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C8051F96x Table 3.1. Pin Definitions for the C8051F96x (Continued) Pin Numbers Name DQFN76 TQFP80 QFN40 P6.4 B10 29 LCD28 P6 LCD29 P6 LCD30 P6 LCD31 42 Type Description D I/O or Port 6.4. See ...
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P0.4/ P0.5/ P0. CNVSTR P4.4/ D1 A40 A39 A38 LCD12 P0. B28 B27 XTAL2 NC P4.5/ P4.6/ P0.2/ LCD13 LCD14 A2 XTAL1 P4.3/ B1 LCD11 P0.1/ A3 AGND P4.2/ B2 LCD10 P0.0/ A4 VREF P4.1/ B3 ...
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C8051F96x P0.4/ P0.5/ P0. CNVSTR P0.3/ 1 XTAL2 P0.2/ 2 XTAL1 P0.1/ 3 AGND P0.0/ 4 VREF VBAT/ 5 VBATDC /VIO IND 6 GND/ 7 GNDDC VDC/ 8 VIORF RST/ 9 C2CK P7.0/ 10 C2D ...
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P0.3/XTAL2 1 P0.2/XTAL1 2 P4.3/LCD11 3 P0.1/AGND 4 P4.2/LCD10 5 P0.0/VREF 6 P4.1/LCD9 7 VBAT 8 VIO 9 VBATDC 10 C8051F960/2/4/6/8 GQ IND 11 GNDDC 12 GND 13 VDC 14 VIORF 15 RST/C2CK 16 P7.0/C2D 17 P6.7/LCD31 ...
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C8051F96x 3.1. DQFN-76 Package Specifications 3.1.1. Package Drawing Figure 3.4. DQFN-76 Package Drawing Table 3.2. DQFN-76 Package Dimensions Dimension Min Typ A 0.74 0.84 b 0.25 0.30 D 6.00 BSC D2 3.00 3.10 e 0.50 BSC E 6.00 BSC ...
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Land Pattern Figure 3.5. DQFN-76 Land Pattern Table 3.3. DQFN-76 Land Pattern Dimensions Symbol Notes: 1. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of ...
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C8051F96x 3.1.3. Soldering Guidelines 3.1.3.1. Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad m minimum, all the way around the pad. 3.1.3.2. ...
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C1 Figure 3.6. Recomended Inner Via Placement Table 3.4. Recomended Inner Via Placement Dimensions Dimension Min C1 — C2 — v — h — Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Via hole should ...
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C8051F96x 3.2. QFN-40 Package Specifications Figure 3.7. Typical QFN-40 Package Drawing Table 3.5. QFN-40 Package Dimensions Dimension Min Typ A 0.80 0.85 A1 0.00 — b 0.18 0.23 D 6.00 BSC D2 4.00 4.10 e 0.50 BSC E 6.00 BSC ...
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Figure 3.8. QFN-40 Landing Diagram Table 3.6. QFN-40 Landing Diagram Dimensions Dimension Min C1 5.80 C2 5.80 e 0.50 BSC X1 0.15 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimension and Tolerancing is ...
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C8051F96x 3.3. TQFP-80 Package Specifications Figure 3.9. TQFP-80 Package Drawing Table 3.7. TQFP-80 Package Dimensions Dimension Min Nominal Max — — 1.20 0.05 — 0.15 0.95 1.00 ...
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Table 3.7. TQFP-80 Package Dimensions Dimension Min ° 0 aaa bbb ccc ddd eee Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This package outline conforms to ...
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C8051F96x Figure 3.10. TQFP80 Landing Diagram Table 3.8. TQFP80 Landing Diagram Dimensions Dimension Notes: 1. All feature sizes shown are in mm unless otherwise noted. 2. This Land Pattern Design is based on the ...
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Soldering Guidelines 3.3.1.1. Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad m minimum, all the way around the pad. 3.3.1.2. Stencil ...
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C8051F96x 4. Electrical Characteristics Throughout the Electrical Characteristics chapter: “VIO” refers to the VIO or VIORF Supply Voltage. 4.1. Absolute Maximum Specifications Table 4.1. Absolute Maximum Ratings Parameter Ambient Temperature under Bias Storage Temperature Voltage on any VIO Port ...
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Electrical Characteristics Table 4.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Supply Voltage (V ) BAT Minimum RAM Data 1 Retention Voltage 2 SYSCLK (System Clock) T (SYSCLK High Time) ...
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C8051F96x Table 4.4. Digital Supply Current with DC-DC Converter Disabled –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Digital Supply Current - Active Mode, No Clock Gating (PCLKACT=0x0F) (CPU Active, fetching instructions from flash ...
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Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Digital Supply Current—Idle Mode (CPU Inactive, not Fetching Instructions from Flash BAT (includes precision oscillator current) ...
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C8051F96x Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Digital Supply Current— Low Power Idle Mode, All peripheral clocks enabled (PCLKEN = 0x0F) (CPU Inactive, not ...
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Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Digital Supply Current—Sleep Mode (LCD Enabled, RTC enabled) Digital Supply Current (Sleep Mode, SmaRTClock running, internal LFO, ...
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C8051F96x Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Digital Supply Current (Sleep Mode, SmaRTClock running, 32.768 kHz Crys- tal, LCD Contrast Mode 3 (2.7 ...
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Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Digital Supply Current—Sleep Mode (LCD disabled, RTC enabled) Digital Supply Current (Sleep Mode, SmaRTClock running, 32.768 kHz crystal) ...
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C8051F96x Figure 4.1. Frequency Sensitivity (External CMOS Clock Active Idle LP Idle (PCLKEN=0x0F) LP Idle (PCLKEN=0x00 Frequency (MHz) Rev. 0 ° ...
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Table 4.5. Port I/O DC Electrical Characteristics V = 1.8 to 3.8 V, –40 to +85 °C unless otherwise specified. IO Parameters Output High Voltage High Drive Strength, PnDRV IOH = –3 mA, Port I/O push-pull IOH = ...
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C8051F96x 3.6 3.3 3 2.7 2.4 2.1 1.8 1.5 1.2 0 3.6 3.3 3 2.7 2.4 2.1 1.8 1.5 1.2 0 Figure 4.2. Typical VOH Curves, 1.8–3 Typical VOH (High Drive Mode) 10 ...
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Typical VOL (High Drive Mode) 1.8 1.5 1.2 0.9 0.6 0.3 0 -80 -70 -60 -50 -40 -30 Load Current (mA) Typical VOL (Low Drive Mode) 1.8 1.5 1.2 0.9 0.6 0 ...
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C8051F96x Table 4.6. Reset Electrical Characteristics V = 1.8 to 3.8 V, –40 to +85 °C unless otherwise specified. BAT Parameter RST Output Low Voltage RST Input High Voltage RST Input Low Voltage RST Input Pullup Current VBAT Monitor Threshold ...
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... Low Power or Precision Osc. Sleep Mode Wake-up Time Table 4.8. Flash Electrical Characteristics V = 1.8 to 3.8 V, –40 to +85 °C unless otherwise specified., BAT Parameter Flash Size C8051F960/1/2/3 C8051F964/5 C8051F966/7 C8051F968/9 Endurance Erase Cycle Time Write Cycle Time Table 4.9. Internal Precision Oscillator Electrical Characteristics V = 1 – ...
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C8051F96x Table 4.11. SmaRTClock Characteristics V = 1 –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. BAT A Parameter Oscillator Frequency (LFO) Table 4.12. ADC0 Electrical Characteristics V = 1.8 to 3.8 V, ...
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Table 4.12. ADC0 Electrical Characteristics (Continued 1.8 to 3.8 V, VREF = 1.65 V (REFSL[1:0] = 11), BAT Parameter Analog Inputs ADC Input Voltage Range Absolute Pin Voltage with respect to GND Sampling Capacitance Input Multiplexer Impedance Power ...
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C8051F96x Table 4.14. Voltage Reference Electrical Characteristics V – = 1 +85 °C unless otherwise specified. BAT Parameter Internal High-Speed Reference (REFSL[1:0] = 11) Output Voltage VREF Turn-on Time Supply Current External Reference (REFSL[1:0] = ...
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Table 4.15. IREF0 Electrical Characteristics V – = 1 +85 °C, unless otherwise specified. BAT Parameter Static Performance Resolution High Current Mode, Source Output Compliance Range Integral Nonlinearity Differential Nonlinearity Offset Error High Current Mode, ...
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C8051F96x Table 4.16. Comparator Electrical Characteristics V = 1.8 to 3.8 V, –40 to +85 °C unless otherwise noted. BAT Parameter Response Time: * Mode 2 1.2 V BAT CM Response Time: * Mode ...
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Table 4.16. Comparator Electrical Characteristics (Continued 1.8 to 3.8 V, –40 to +85 °C unless otherwise noted. BAT Parameter Hysteresis Mode 0 Hysteresis 1 Hysteresis 2 Hysteresis 3 Hysteresis 4 Mode 1 Hysteresis 1 Hysteresis 2 Hysteresis 3 ...
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C8051F96x Table 4.18. LCD0 Electrical Characteristics V = 1 –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. BAT A Parameter Charge Pump Output Voltage Error LCD Clock Frequency Table 4.19. PC0 Electrical Characteristics ...
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Table 4.20. DC0 (Buck Converter) Electrical Characteristics V = 1 –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. BAT A Parameter Input Voltage Range Input Supply to Output Voltage Differential (for ...
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C8051F96x 5. SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode The ADC0 on C8051F96x devices is a 300 ksps, 10-bit or 75 ksps, 12-bit successive-approximation-regis- ter (SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 ...
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Input Voltage Right-Justified ADC0H:ADC0L VREF x 1023/1024 VREF x 512/1024 VREF x 256/1024 0 When the repeat count is greater than 1, the output conversion code represents the accumulated result of the conversions performed and is updated after the last ...
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C8051F96x 5.2. Modes of Operation ADC0 has a maximum conversion speed of 300 ksps in 10-bit mode. The ADC0 conversion clock (SAR- CLK divided version of the system clock when burst mode is disabled (BURSTEN = 0), or ...
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A. ADC0 Timing for External Trigger Source CNVSTR (AD0CM[2:0]=100) SAR Clocks Low Power AD0TM=1 or Convert AD0TM=0 Track or Convert B. ADC0 Timing for Internal Trigger Source Write '1' to AD0BUSY, Timer 0, Timer 2, Timer 1, Timer 3 Overflow ...
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C8051F96x 5.2.3. Burst Mode Burst Mode is a power saving feature that allows ADC0 to remain in a low power state between conver- sions. When Burst Mode is enabled, ADC0 wakes from a low power state, accumulates ...
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Settling Time Requirements A minimum amount of tracking time is required before each conversion can be performed, to allow the sampling capacitor voltage to settle. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any ...
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C8051F96x 5.3. 8-Bit Mode Setting the ADC08BE bit in register ADC0CF to 1 will put the ADC in 8-bit mode.In 8-bit mode, only the 8 MSBs of data are converted, allowing the conversion to be completed in two fewer SAR ...
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Low Power Mode The SAR converter provides a low power mode that allows a significant reduction in operating current when operating at low SAR clock frequencies. Low power mode is enabled by setting the AD0LPM bit (ADC0PWR. ...
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C8051F96x SFR Definition 5.1. ADC0CN: ADC0 Control Bit 7 6 Name AD0EN BURSTEN AD0INT Type R/W R/W Reset 0 0 SFR Page = All Pages; SFR Address = 0xE8; bit-addressable; Bit Name 7 AD0EN ADC0 Enable. 0: ADC0 Disabled (low-power ...
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SFR Definition 5.2. ADC0CF: ADC0 Configuration Bit 7 6 Name AD0SC[4:0] Type Reset 1 1 SFR Page = 0x0; SFR Address = 0xBC Bit Name 7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Divider. SAR Conversion clock is derived from FCLK by ...
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C8051F96x SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration Bit 7 6 Name AD012BE AD0AE Type R/W W Reset 0 0 SFR Page = 0x0; SFR Address = 0xBA Bit Name 7 AD012BE ADC0 12-Bit Mode Enable. Enables 12-bit Mode. 0: ...
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SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time Bit 7 6 Name AD0LPM Type R/W R Reset 0 0 SFR Page = 0xF; SFR Address = 0xBA Bit Name 7 AD0LPM ADC0 Low Power Mode Enable. Enables Low Power ...
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C8051F96x SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time Bit 7 6 Name Type R R Reset 0 0 SFR Page = 0xF; SFR Address = 0xBB Bit Name 7 Reserved Read = 0b; Write = Must Write 0b. ...
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SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte Bit 7 6 Name Type Reset 0 0 SFR Page = 0x0; SFR Address = 0xBE Bit Name Description 7:0 ADC0[15:8] ADC0 Data Word High Byte. Note: If Accumulator shifting is ...
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C8051F96x SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte Bit 7 6 Name Type Reset 1 1 SFR Page = 0x0; SFR Address = 0xC4 Bit Name 7:0 AD0GT[15:8] ADC0 Greater-Than High Byte. Most Significant Byte of the 16-bit Greater-Than ...
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SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte Bit 7 6 Name Type Reset 0 0 SFR Page = 0x0; SFR Address = 0xC6 Bit Name 7:0 AD0LT[15:8] ADC0 Less-Than High Byte. Most Significant Byte of the 16-bit Less-Than window ...
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C8051F96x ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (1023/1024) 0x03FF AD0WINT not affected 0x0081 VREF x (128/1024) 0x0080 ADC0LTH:ADC0LTL 0x007F 0x0041 VREF x (64/1024) 0x0040 ADC0GTH:ADC0GTL 0x003F AD0WINT not affected 0x0000 0 Figure 5.5. ADC Window Compare Example: Right-Justified ...
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ADC0 Analog Multiplexer ADC0 on C8051F96x has an analog multiplexer, referred to as AMUX0. AMUX0 selects the positive inputs to the single-ended ADC0. Any of the following may be selected as the positive input: Port I/O pins, the on-chip ...
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C8051F96x SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select Bit 7 6 Name R R Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xBB Bit Name 7:5 Unused Read = 000b; Write = Don’t Care. 4:0 AD0MX ...
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Temperature Sensor An on-chip temperature sensor is included on the C8051F96x which can be directly accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the temperature sensor, the ADC mux channel should select the ...
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C8051F96x Figure 5.9 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Parame- ters that affect ADC measurement, in particular the voltage reference value, will also affect temper- ature measurement. A single-point offset measurement of the ...
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SFR Definition 5.13. TOFFH: Temperature Sensor Offset High Byte Bit 7 6 Name Type R R Reset Varies Varies Varies SFR Page = 0xF; SFR Address = 0xBE Bit Name 7:0 TOFF[9:2] Temperature Sensor Offset High Bits. Most Significant Bits ...
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C8051F96x 5.9. Voltage and Ground Reference Options The voltage reference MUX is configurable to use an externally connected voltage reference, the internal voltage reference, or one of two power supply voltages (see Figure 5.10). The ground reference MUX allows the ...
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External Voltage Reference To use an external voltage reference, REFSL[1:0] should be set to 00. Bypass capacitors should be added as recommended by the manufacturer of the external voltage reference. If the manufacturer does not pro- vide recommendations, a ...
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C8051F96x SFR Definition 5.15. REF0CN: Voltage Reference Control Bit 7 6 Name REFGND R R Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xD1 Bit Name 7:6 Unused Read = 00b; Write = Don’t Care. 5 REFGND ...
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Programmable Current Reference (IREF0) C8051F96x devices include an on-chip programmable current reference (source or sink) with two output current settings: Low Power Mode and High Current Mode. The maximum current output in Low Power Mode is 63 µA (1 ...
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C8051F96x SFR Definition 6.2. IREF0CF: Current Reference Configuration Bit 7 6 Name PWMEN Type R/W R/W Reset 0 0 SFR Page = 0xF; SFR Address = 0xB9 Bit Name 7 PWMEN PWM Enhanced Mode Enable. Enables the PWM Enhanced Mode. ...
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Comparators C8051F96x devices include two on-chip programmable voltage comparators: Comparator 0 (CPT0) is shown in Figure 7.1; Comparator 1 (CPT1) is shown in Figure 7.2. The two comparators operate identi- cally, but may differ in their ability to be ...
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C8051F96x 7.2. Comparator Outputs When a comparator is enabled, its output is a logic 1 if the voltage at the positive input is higher than the voltage at the negative input. When disabled, the comparator output is a logic 0. ...
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Comparator Response Time Comparator response time may be configured in software via the CPTnMD registers described on “CPT0MD: Comparator 0 Mode Selection” on page 109 and “CPT1MD: Comparator 1 Mode Selection” on page 111. Four response time settings are ...
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C8051F96x 7.5. Comparator Register Descriptions The SFRs used to enable and configure the comparators are described in the following register descrip- tions. A Comparator must be enabled by setting the CPnEN bit to logic 1 before it can be used. ...
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SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection Bit 7 6 Name CP0RIE R/W R Type 1 0 Reset SFR Page = 0x0; SFR Address = 0x9D Bit Name 7 Reserved Read = 1b, Must Write 1b. 6 Unused Read ...
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C8051F96x SFR Definition 7.3. CPT1CN: Comparator 1 Control Bit 7 6 Name CP1EN CP1OUT CP1RIF R/W R Type 0 0 Reset SFR Page= 0x0; SFR Address = 0x9A Bit Name 7 CP1EN Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 ...
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SFR Definition 7.4. CPT1MD: Comparator 1 Mode Selection Bit 7 6 Name CP1RIE R/W R Type 1 0 Reset SFR Page = 0x0; SFR Address = 0x9C Bit Name 7 Reserved Read = 1b, Must Write 1b. 6 Unused Unused. ...
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C8051F96x 7.6. Comparator0 and Comparator1 Analog Multiplexers Comparator0 and Comparator1 on C8051F96x devices have analog input multiplexers to connect Port I/O pins and internal signals the comparator inputs; CP0+/CP0- are the positive and negative input multiplex- ers for Comparator0 and ...
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SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select Bit 7 6 CMX0N[3:0] Name R/W R/W Type 1 1 Reset SFR Page = 0x0; SFR Address = 0x9F Bit Name 7:4 CMX0N Comparator0 Negative Input Selection. Selects the negative input channel ...
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C8051F96x SFR Definition 7.6. CPT1MX: Comparator1 Input Channel Select Bit 7 6 CMX1N[3:0] Name R/W R/W Type 1 1 Reset SFR Page = 0x0; SFR Address = 0x9E Bit Name 7:4 CMX1N Comparator1 Negative Input Selection. Selects the negative input ...
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CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset ...
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... This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or other on-chip resources. C2 details can be found in Section “34. C2 Interface” on page 486. The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro- vides an integrated development environment (IDE) including editor, debugger and programmer. The IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-sys- tem device programming and debugging ...
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Table 8.1. CIP-51 Instruction Set Summary Mnemonic ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to A ADDC A, Rn ...
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C8051F96x Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic CLR A Clear A CPL A Complement Rotate A left RLC A Rotate A left through Carry RR A Rotate A right RRC A Rotate A right through ...
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Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic ANL C, /bit AND complement of direct bit to Carry ORL C, bit OR direct bit to carry ORL C, /bit OR complement of direct bit to Carry MOV C, bit Move ...
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C8051F96x Notes on Registers, Operands and Addressing Modes: Rn—Register R0–R7 of the currently selected register bank. @Ri—Data RAM location addressed indirectly through R0 or R1. rel—8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used ...
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CIP-51 Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in which ...
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C8051F96x SFR Definition 8.3. SP: Stack Pointer Bit 7 6 Name Type 0 0 Reset SFR Page = All Pages; SFR Address = 0x81 Bit Name 7:0 SP[7:0] Stack Pointer. The Stack Pointer holds the location of the top of ...
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SFR Definition 8.6. PSW: Program Status Word Bit Name R/W R/W Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xD0; Bit-Addressable Bit Name 7 CY Carry Flag. This bit is set when ...
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... Figure 9.1. C8051F96x Memory Map 9.1. Program Memory The C8051F960/1/2/3 device flashs have a 128 kB program memory space, C8051F964/5 devices have 64 kB program memory space, C8051F966/7 devices have 32 kB program memory space, and C8051F968/9 devices have program memory space. The devices with 128 kB flash implement this program memory space as in-system re-programmable flash memory in four 32 kB code banks ...
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... The IFBANK bits select which of the upper banks are used for code execution, while the COBANK bits select the bank to be used for direct writes and reads of the flash memory. The address 0x1FFFF (C8051F960/1/2/3), 0xFFFF (C8051F964/5), 0x07FFF (C8051F966/7), or 0x3FFF (C8051F9608/9) serves as the security lock byte for the device. Any addresses above the lock byte are reserved ...
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C8051F96x Internal IFBANK = 0 Address 0 xFFFF Bank 0 0x 8000 0x7FFF Bank 0 0x 0000 Figure 9.3. Address Memory Map for Instruction Fetches 126 IFBANK = 1 IFBANK = 2 Bank 1 Bank 2 Bank 0 Bank 0 ...
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SFR Definition 9.1. PSBANK: Program Space Bank Select Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Page = All Pages; SFR Address = 0x84 Bit Name 7:6 Reserved Read = 00b, Must Write = 00b. 5:4 COBANK[1:0] ...
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C8051F96x 9.2.1. Internal RAM There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct ...
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External Data Memory Interface and On-Chip XRAM For C8051F96x devices RAM are included on-chip and mapped into the external data memory space (XRAM). Additionally, an External Memory Interface (EMIF) is available on the C8051F960/2/4/6/8 devices, which ...
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C8051F96x 10.2. Configuring the External Memory Interface Configuring the External Memory Interface consists of five steps: 1. Configure the Output Modes of the associated port pins as either push-pull or open-drain (push-pull is most common). The Input Mode of the ...
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Table 10.1. EMIF Pinout (C8051F960/2/4/6/8) Multiplexed Mode Signal Name Port Pin 1 8-Bit Mode 16-Bit Mode RD P3.6 WR P3.7 ALE P3.5 AD0 P6.0 AD1 P6.1 AD2 P6.2 AD3 P6.3 AD4 P6.4 AD5 P6.5 AD6 P6.6 AD7 P6.7 A8 — ...
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C8051F96x SFR Definition 10.1. EMI0CN: External Memory Interface Control Bit 7 6 Name Type Reset 0 0 SFR Page = 0x0; SFR Address = 0xAA Bit Name 7:0 PGSEL[7:0] XRAM Page Select Bits. The XRAM Page Select Bits provide the ...
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SFR Definition 10.2. EMI0CF: External Memory Configuration Bit 7 6 Name Type Reset 0 0 SFR Page = 0x0; SFR Address = 0xAB Bit Name 7:5 Unused Read = 000b; Write = Don’t Care. 4 EMD2 EMIF Multiplex Mode Select ...
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C8051F96x 10.4. Multiplexed and Non-multiplexed Selection The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode, depending on the state of the EMD2 (EMI0CF.4) bit. 10.4.1. Multiplexed Configuration In Multiplexed mode, the Data Bus ...
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A[15: D[7: Figure 10.2. Non-multiplexed Configuration Example 10.5. Memory Mode Selection The external data memory space can be configured in one of four modes, shown in Figure 10.3, based on the EMIF Mode bits ...
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C8051F96x 10.5.1. Internal XRAM Only When bits EMI0CF[3:2] are set to 00, all MOVX instructions will target the internal XRAM space on the device. Memory accesses to addresses beyond the populated space will wrap boundaries ...
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Timing The timing parameters of the External Memory Interface can be configured to enable connection to devices having different setup and hold time requirements. The Address Setup time, Address Hold time, RD and WR strobe widths, and in multiplexed ...
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C8051F96x SFR Definition 10.3. EMI0TC: External Memory Timing Control Bit 7 6 Name EAS[1:0] Type R/W Reset 1 1 SFR Page = 0x0; SFR Address = 0xAF Bit Name 7:6 EAS[1:0] EMIF Address Setup Time Bits. 00: Address setup time ...
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Non-Multiplexed Mode 10.6.1.1. 16-bit MOVX: EMI0CF[4:2] = 101, 110, or 111 ADDR[15:8] ADDR[7:0] DATA[7: ADDR[15:8] P2 ADDR[7:0] DATA[7: Figure 10.4. Non-multiplexed 16-bit MOVX Timing Nonmuxed 16-bit WRITE EMIF ADDRESS (8 MSBs) from DPH EMIF ADDRESS ...
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C8051F96x 10.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 101 or 111 ADDR[15:8] ADDR[7:0] DATA[7: ADDR[15:8] ADDR[7:0] DATA[7: Figure 10.5. Non-multiplexed 8-bit MOVX without Bank Select Timing 140 Nonmuxed 8-bit WRITE without Bank Select EMIF ADDRESS ...
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MOVX with Bank Select: EMI0CF[4:2] = 110 ADDR[15:8] ADDR[7:0] DATA[7: ADDR[15:8] ADDR[7:0] DATA[7: Figure 10.6. Non-multiplexed 8-bit MOVX with Bank Select Timing Nonmuxed 8-bit WRITE with Bank Select EMIF ADDRESS (8 MSBs) from EMI0CN ...
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C8051F96x 10.6.2. Multiplexed Mode 10.6.2.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] T ALEH ALE WR RD ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] T ALEH ALE RD WR Figure 10.7. Multiplexed ...
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MOVX without Bank Select: EMI0CF[4:2] = 001 or 011 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE WR RD ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE RD ...
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C8051F96x 10.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 010 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE WR RD ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE RD WR ...
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Table 10.2. AC Parameters for External Memory Interface Parameter Description T Address/Control Setup Time ACS T Address/Control Pulse Width ACW T Address/Control Hold Time ACH T Address Latch Enable High Time ALEH T Address Latch Enable Low Time ALEL T ...
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C8051F96x 11. Direct Memory Access (DMA0) An on-chip direct memory access (DMA0) is included on the C8051F96x devices. The DMA0 subsystem allows autonomous variable-length data transfers between XRAM and peripheral SFR registers without CPU intervention. During DMA0 operation, the CPU ...
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Peripheral assignment - DMA0nCF[2:0] XRAM to ENC0 request ENC0 to XRAM request XRAM to CRC1 request XRAM to SPI1 request SPI1 to XRAM request XRAM to AES0KIN request XRAM to AES0BIN request XRAM to AES0XIN request AES0YOUT to XRAM request ...
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C8051F96x Data transfer size DMA0NSZH:L defines the maximum number of bytes for the DMA0 transfer of the selected channel. If the address offset reaches data transfer size, the full-length interrupt flag bit CHn_INT (DMA0INT) of the selected channel will be ...
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Transfer Configuration The following steps are required to configure one of the DMA0 channels for operation: 1. Select the channel to be configured by writing DMA0SEL. 2. Specify the data transfer function by writing DMA0NCF. This register also specifies ...
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C8051F96x SFR Definition 11.1. DMA0EN: DMA0 Channel Enable Bit 7 6 Name CH6_EN Type R R/W Reset 0 0 SFR Page = 0x2; SFR Address = 0xD2 Bit Name 7 Unused Read = 0b, Write = Don’t Care 6 CH6_EN ...
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SFR Definition 11.2. DMA0INT: DMA0 Full-Length Interrupt Bit 7 6 Name CH6_INT CH5_INT CH4_INT CH3_INT CH2_INT CH1_INT CH0_INT Type R R/W Reset 0 0 SFR Page = 0x2; SFR Address = 0xD3 Bit Name 7 Unused Read = 0b, Write ...
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C8051F96x SFR Definition 11.3. DMA0MINT: DMA0 Mid-Point Interrupt Bit 7 6 Name CH6_MINT CH5_MINT CH4_MINT CH3_MINT CH2_MINT CH1_MINT CH0_MINT Type R R/W Reset 0 0 SFR Page = 0x2; SFR Address = 0xD4 Bit Name 7 Unused Read = 0b, ...
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SFR Definition 11.4. DMA0BUSY: DMA0 Busy Bit 7 6 Name CH6_BUSY CH5_BUSY CH4_BUSY CH3_BUSY CH2_BUSY CH1_BUSY CH0_BUSY Type R R/W R/W Reset 0 0 SFR Page = 0x2; SFR Address = 0xD5 Bit Name Description 7 Unused 6 CH6_BUSY Channel ...
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C8051F96x SFR Definition 11.5. DMA0SEL: DMA0 Channel Select for Configuration Bit 7 6 Name Type R R/W Reset 0 0 SFR Page = 0x2; SFR Address = 0xD1 Bit Name 7:3 Unused Read = 0b, Write = Don’t Care 2:0 ...
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SFR Definition 11.6. DMA0NMD: DMA Channel Mode Bit 7 6 Name Type R/W R/W Reset 0 0 SFR Page = 0x2; SFR Address = 0xD6 Bit Name 7:1 reserved Read = 0, Write = 0 0 WRAP Wrap Enable. Setting ...
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C8051F96x SFR Definition 11.7. DMA0NCF: DMA Channel Configuration Bit 7 6 Name INTEN MINTEN Type R/W R/W Reset 0 0 SFR Page = 0x2; SFR Address = 0xC9 Bit Name 7 INTEN Full-Length Interrupt Enable. 0: Disable the full-length interrupt ...
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SFR Definition 11.8. DMA0NBAH: Memory Base Address High Byte Bit 7 6 Name Type R R Reset 0 0 SFR Page = 0x2; SFR Address = 0xCB Bit Name 7:4 Unused Read = 0b, Write = Don’t Care 3:0 NBAH[3:0] ...
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C8051F96x SFR Definition 11.10. DMA0NAOH: Memory Address Offset High Byte Bit 7 6 Name Type R R Reset 0 0 SFR Page = 0x2; SFR Address = 0xCD Bit Name 7:2 Unused Read = 0b, Write = Don’t Care 1:0 ...
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SFR Definition 11.12. DMA0NSZH: Transfer Size High Byte Bit 7 6 Name Type R R Reset 0 0 SFR Page = 0x2; SFR Address = 0xCF Bit Name 7:2 Unused Read = 0b, Write = Don’t Care 1:0 NSZH[1:0] Transfer ...
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C8051F96x 12. Cyclic Redundancy Check Unit (CRC0) C8051F96x devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a 16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0 ...
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The 16-bit C8051F96x CRC algorithm can be described by the following code: unsigned short UpdateCRC (unsigned short CRC_acc, unsigned char CRC_input) { unsigned char i; #define POLY 0x1021 // Create the CRC "dividend" for polynomial arithmetic (binary arithmetic // with ...
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C8051F96x 12.2. 32-bit CRC Algorithm The C8051F41x CRC unit calculates the 32-bit CRC using a poly of 0x04C11DB7. The CRC-32 algorithm is "reflected", meaning that all of the input bytes and the final 32-bit output are bit-reversed in the process- ...
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Table 12.2. Example 32-bit CRC Outputs Input 0x63 0xAA, 0xBB, 0xCC 0x00, 0x00, 0xAA, 0xBB, 0xCC 12.3. Preparing for a CRC Calculation To prepare CRC0 for a CRC calculation, software should select the desired polynomial and set the initial value ...
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C8051F96x SFR Definition 12.1. CRC0CN: CRC0 Control Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Page = 0xF; SFR Address = 0x92 Bit Name 7:5 Unused Read = 000b; Write = Don’t Care. 4 CRC0SEL CRC0 Polynomial ...
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SFR Definition 12.2. CRC0IN: CRC0 Data Input Bit 7 6 Name Type 0 0 Reset SFR Page = 0xF; SFR Address = 0x93 Bit Name 7:0 CRC0IN[7:0] CRC0 Data Input. Each write to CRC0IN results in the written data being ...
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C8051F96x SFR Definition 12.4. CRC0AUTO: CRC0 Automatic Control Bit 7 6 AUTOEN CRCDONE Name Type 0 1 Reset SFR Page = 0xF; SFR Address = 0x96 Bit Name 7 AUTOEN Automatic CRC Calculation Enable. When AUTOEN is set to 1, ...
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CRC0 Bit Reverse Feature CRC0 includes hardware to reverse the bit order of each bit in a byte as shown in Figure 12.2. Each byte of data written to CRC0FLIP is read back bit reversed. For example, if 0xC0 ...
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C8051F96x 13. DMA-Enabled Cyclic Redundancy Check Module (CRC1) C8051F96x devices include a DMA-enabled cyclic redundancy check module (CRC1) that can perform a CRC of data using an arbitrary 16-bit polynomial. This peripheral can compute CRC results using direct DMA access ...
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Endianness The CRC1 module is optimized to process big endian data. Data written to the CRC1IN SFR should be in the normal bit order with the most significant bit stored in bit 7 and the least significant bit stored ...
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C8051F96x 13.3. CRC Seed Value Normally, the initial value or the CRC results is cleared to 0x0000. However, a CRC might be specified with an initial value preset to all ones (0xFFFF). The steps to preset the CRC with all ...
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Using CRC1 with SFR Access The steps to perform a CRC using SFR access with the CRC1 module is as follow desired, set the SEED bit in the CRC1CN SFR to seed with 0xFFFF. 2. Clear the ...
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C8051F96x SFR Definition 13.1. CRC1CN: CRC1 Control Bit 7 6 CLR Name R/W R Type 0 0 Reset SFR Page = 0x2; SFR Address = 0xBE; Not Bit-Addressable Bit Name 7 RST Reset. Setting this bit to 1 will reset ...
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SFR Definition 13.2. CRC1IN: CRC1 Data IN Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Page = 0x2; SFR Address = 0xB9; Not Bit-Addressable Bit Name 7:0 CRC1IN[7:0] CRC1Data IN. CRC Data should be sequentially written, one ...
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C8051F96x SFR Definition 13.5. CRC1OUTL: CRC1 Output LSB Bit 7 6 Name R R Type 0 0 Reset SFR Page = 0x2; SFR Address = 0xBA; Not Bit-Addressable Bit Name 7:0 CRC1OUTL[7:0] CRC1 Output LSB SFR Definition 13.6. CRC1OUTH: CRC1 ...
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Advanced Encryption Standard (AES) Peripheral The C8051F96x includes a hardware implementation of the Advanced Encryption Standard Block Cipher as specified in NIST publication FIPS 197 “Advanced Encryption Standard (AES), November 2001. The Rijndael encryption algorithm was chosen by NIST ...
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C8051F96x 14.1. Hardware Description internal state machine AES0DCF AES0KIN AES0BCFG Figure 14.1. AES Peripheral Block Diagram The AES Encryption module consists of these elements. AES Encryption/Decryption Core Configuration sfrs Key input sfr Data sfrs Input ...
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AES Encryption/Decryption Core The AES Encryption/Decryption Core is a digital implementation of the Advanced Encryption Standard block cipher. The core may be used for either encryption or decryption. Encryption may be selected by set- ting bit 5 in the ...
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C8051F96x 14.1.3. Configuration sfrs The AES Module has two configuration sfrs. The AES0BCFG sfr is used to configure the AES core. Bits 0 and 1 are used to select the Key size. The AES core supports 128-bit, 192-bit and 256-bit ...
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Key Inversion The Key output is used to generate an inverse key. To generate a decryption key from an encryption key, the AES core should be configured for an encryption operation. Dummy data and the encryption key are written ...
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C8051F96x 14.2.1. Key Inversion using DMA Normally, the AES block is used with the DMA. This provides the best performance and lowest power con- sumption. Code examples are provided in 8051 compiler independent C code using the DMA ...
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The key and data to be encrypted should be stored as an array with the first byte to be encrypted at the lowest address. The value of the big endian bit of the DMACF0 sfr does not matter. The AES ...
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C8051F96x 14.2.3. Extended Key Output Byte Order When using a key length of 128-bits, the key output is in the same order as the bytes were written. When using an extended key of 192-bits or 256-bits. The extended portion of ...
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Using the DMA to unwrap the extended Key When used with the DMA, the address offset sfr DMANAOH/L may be manipulated to store the extended key in the desired order. This requires two DMA transfers for the AES0YOUT channel. ...
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C8051F96x 14.3. AES Block Cipher The basic AES Block Cipher is the basic encryption/decryption algorithm as defined by the NIST standard. A clock cipher mode is a method of encrypting and decrypting one block of data. The input data and ...
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AES Block Cipher Data Flow The AES0 module data flow for AES Block Cipher encryption and decryption shown in Figure 14.3. The data flow is the same for encryption and decryption. The AES0DCF sfr is always configured to route ...
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C8051F96x 14.4.1. AES Block Cipher Encryption using DMA Normally, the AES block is used with the DMA. This provides the best performance and lowest power con- sumption. Code examples are provided in 8051 compiler independent C code using the DMA. ...
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AES Block Cipher Encryption using SFRs First Configure AES Module for AES Block Cipher Reset AES module by writing 0x00 to AES0BCFG. Configure the AES Module data flow for AES Block Cipher by writing 0x00 to the ...
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C8051F96x 14.5. AES Block Cipher Decryption 14.5.1. AES Block Cipher Decryption using DMA Normally, the AES block is used with the DMA. This provides the best performance and lowest power con- sumption. Code examples are provided in 8051 compiler independent ...
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AES Block Cipher Decryption using SFRs First Configure AES Module for AES Block Cipher Reset AES module by writing 0x00 to AES0BCFG. Configure the AES Module data flow for AES Block Cipher by writing 0x00 to the ...
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C8051F96x 14.6. Block Cipher Modes 14.6.1. Cipher Block Chaining Mode The Cipher Block Chaining (CBC) Mode algorithm significantly improves the strength of basic AES encryp- tion by making each block encryption be a function of the previous block in addition ...
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CBC Encryption Data Flow The AES0 module data flow for CBC encryption is shown in Figure 14.5. The plaintext is written to the AES0BIN sfr. For the first block, the initialization vector is written to the AES0XIN sfr. For ...
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C8051F96x 14.6.2. CBC Encryption Initialization Vector Location The first block to be encrypted uses the initialization vector for the AES0XIN data. Subsequent blocks will use the encrypted ciphertext from the previous block. The DMA is capable of encrypting multiple bocks. ...
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Enable first four DMA channels setting bits the DMA0EN sfr Configure the AES Module data flow for XOR on input data by writing 0x01 to the AES0DCFG sfr. Write key size to bits ...
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C8051F96x 14.6.3.1. CBC Encryption using SFRs First Configure AES Module for CBC Block Cipher Mode Encryption Reset AES module by writing 0x00 to AES0BCFG. Configure the AES Module data flow for XOR on input data by writing 0x01 ...
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CBC Decryption The AES0 module data flow for CBC encryption is shown in Figure 14.6. The ciphertext is written to the AES0BIN sfr. For the first block, the initialization vector is written to the AES0XIN sfr. For subsequent blocks, ...
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C8051F96x 14.6.4.1. CBC Decryption using DMA Normally, the AES block is used with the DMA. This provides the best performance and lowest power con- sumption. Code examples are provided in 8051 compiler independent C code using the DMA ...
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CBC Decryption using SFRs First Configure AES Module for CBC Block Cipher Mode Decryption Reset AES module by writing 0x00 to AES0BCFG. Configure the AES Module data flow for XOR on output data by writing 0x02 to ...
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C8051F96x 14.6.5. Counter Mode The Counter (CTR) Mode uses a sequential counter which is incremented after each block. This turns the block cipher into a stream cipher. This algorithm is shown inFigure 14.4. Note that the decryption operation actually uses ...
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CTR Data Flow The AES0 module data flow for CTR encryption and decryption shown in Figure 14.5. The data flow is the same for encryption and decryption. The AES0DCF sfr is always configured to XOR AES0XIN with the AES ...
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C8051F96x 14.6.6. CTR Encryption using DMA Normally, the AES block is used with the DMA. This provides the best performance and lowest power con- sumption. Code examples are provided in 8051 compiler independent C code using the DMA ...