C8051F964-A-GQ Silicon Labs, C8051F964-A-GQ Datasheet - Page 266
C8051F964-A-GQ
Manufacturer Part Number
C8051F964-A-GQ
Description
8-bit Microcontrollers - MCU 64KB DC-DC LCD AES
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F964-A-GQ
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
24.5 MHz
Program Memory Size
64 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.8 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
Available stocks
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Quantity:
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C8051F96x
SFR Definition 19.5. PMU0FL: Power Management Unit Flag
SFR Page = 0x0; SFR Address = 0xB6
266
Notes:
Name
Reset
7:3
Bit
Type
2
1
0
Bit
1. The Low Power Internal Oscillator cannot be disabled and the MCU cannot be placed in suspend or sleep
2. PMU0 requires two system clocks to update the wake-up source flags after waking from suspend mode. The
mode if any wake-up flags are set to 1. Software should clear all wake-up sources after each reset and after
each wake-up from Suspend or Sleep Modes.
wake-up source flags will read 0 during the first two system clocks following the wake from suspend mode.
BATMWK
Reserved
CS0WK
Unused
Name
R
7
0
Unused
VBAT Monitor (inside
LCD Logic) Wake-up
Source Enable and Flag
Reserved
Pulse Counter Wake-up
Source Enable and Flag
R
6
0
Description
R
5
0
Rev. 0.5
Don’t Care.
0: Disable wake-up on
VBAT Monitor event.
1: Enable wake-up on CS0
event.
Must write 0.
0: Disable wake-up on
PC0 event.
1: Enable wake-up on PC0
event.
R
4
0
Write
R
3
0
BATMWK
R/W
2
0
1,2
0000000
Set to 1 if VBAT Monitor
event caused the last
wake-up.
Always reads 0.
Set to 1 if PC0 event
caused the last wake-up.
Reserved
R/W
1
0
Read
PC0WK
Varies
R/W
0
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