LPC1113FHN33/203,5 NXP Semiconductors, LPC1113FHN33/203,5 Datasheet - Page 360
LPC1113FHN33/203,5
Manufacturer Part Number
LPC1113FHN33/203,5
Description
ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1113FHN333035.pdf
(538 pages)
Specifications of LPC1113FHN33/203,5
Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1113
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
24 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Factory Pack Quantity
260
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Table 318: Match Control Register (TMR32B0MCR - address 0x4001 4014 and TMR32B1MCR - address 0x4001 8014)
Table 320: Capture Control Register (TMR32B0CCR - address 0x4001 4028 and TMR32B1CCR - address
UM10398
User manual
Bit
9
10
11
31:12
Bit
0
Symbol
CAP0RE
Symbol Value Description
MR3I
MR3R
MR3S
-
bit description
0x4001 8028) bit description
20.7.7 Match Registers (TMR32B0MR0/1/2/3 - addresses 0x4001
20.7.8 Capture Control Register (TMR32B0CCR and TMR32B1CCR)
1
0
1
0
1
0
Value Description
1
0
4018/1C/20/24 and TMR32B1MR0/1/2/3 addresses 0x4001
8018/1C/20/24)
The Match register values are continuously compared to the Timer Counter value. When
the two values are equal, actions can be triggered automatically. The action possibilities
are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are
controlled by the settings in the MCR register.
Table 319: Match registers (TMR32B0MR0 to 3, addresses 0x4001 4018 to 24 and
The Capture Control Register is used to control whether the Capture Register is loaded
with the value in the Timer Counter when the capture event occurs, and whether an
interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
description below, “n” represents the Timer number, 0 or 1.
Bit
31:0
Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
Enabled
Disabled
Reset on MR3: the TC will be reset if MR3 matches it.
Enabled
Disabled
Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches
the TC.
Enabled
Disabled
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will
cause CR0 to be loaded with the contents of TC.
Enabled
Disabled
Symbol
MATCH
TMR32B1MR0 to 3, addresses 0x4001 8018 to 24) bit description
Chapter 20: LPC1100/LPC1100C/LPC1100L series: 32-bit counter/timer
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Description
Timer counter match value.
UM10398
© NXP B.V. 2012. All rights reserved.
360 of 538
Reset
value
0
0
0
Reset
value
0
NA
Reset
value
0
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