MK22DX256VLH5 Freescale Semiconductor, MK22DX256VLH5 Datasheet - Page 45

• Manufacturer Part Number: MK22DX256VLH5
• Description: ARM Microcontrollers - MCU ARM+256Kb +USB
• Manufacturer: Freescale Semiconductor

Specifications of MK22DX256VLH5

• Rohs: yes
• Core: ARM Cortex M4
• Processor Series: MK22DX256
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT

4.5.7.9 Secure Digital Host Controller (SDHC)
4.5.7.10 Synchronous Serial Interface (I
Freescale Semiconductor, Inc.
• Address match feature in receiver to reduce address mark wakeup ISR overhead
• Hardware flow control support for request to send (RTS) and clear to send (CTS) signals
• Support for CEA709.1-B protocol (LON) used in building automation and home networking systems
• Interrupt or DMA driven operation
• Receiver framing error detection
• Hardware parity generation and checking
• 1/16 bit-time noise detection
• Compatible with the following specifications:
• Designed to work with CE-ATA, SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC, MMCplus, and
• SD bus clock frequency up to 50 MHz
• Supports 1-/4-bit SD and SDIO modes, 1-/4-/8-bit MMC modes, 1-/4-/8-bit CE-ATA devices
• Up to 200 Mbps data transfer for SD/SDIO cards using four parallel data lines
• Up to 416 Mbps data transfer for MMC using 8 parallel data lines
• Single- and multi-block read and write
• 1-4096 byte block size
• Write-protection switch for write operations
• Synchronous and asynchronous abort
• Pause during the data transfer at a block gap
• SDIO read wait and suspend/resume operations
• Auto CMD12 for multi-block transfer
• Host can initiate non-data transfer commands while the data transfer is in progress
• Allows cards to interrupt the host in 1- and 4-bit SDIO modes
• Supports interrupt period, defined in the SDIO standard
• Fully configurable 128 x 32-bit FIFO for read/write data
• Internal DMA capabilities
• Supports voltage selection by configuring vendor specific register bit
• Supports advanced DMA to perform linked memory access
• Independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared internal/
• Master or slave mode operation
• Normal mode operation using frame sync
• Network mode operation allowing multiple devices to share the port with up to 32 time slots
• Programmable data interface modes, such as I
• Programmable word length (8, 10, 12, 16, 18, 20, 22 or 24 bits)
• AC97 support
RS-MMC cards
external clocks and frame syncs, operating in master or slave mode intended for audio support
• Idle line wakeup
• Address mark wakeup
• SD Host Controller Standard Specification, Version 2.0
• MultiMediaCard System Specification, Version 4.2
• SD Memory Card Specification, Version 2.0
• SDIO Card Specification, Version 2.0
• CE-ATA Card Specification, Version 1.0
advanced DMA support
cards
K20 Family Product Brief, Rev. 11, 08/2012
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), supporting high capacity SD memory
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Communication interfaces
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