LPC1112FHI33/202,5 NXP Semiconductors, LPC1112FHI33/202,5 Datasheet - Page 46
LPC1112FHI33/202,5
Manufacturer Part Number
LPC1112FHI33/202,5
Description
ARM Microcontrollers - MCU CortexM0 32bit 16KB up to 4 kB SRAM
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1114FN2810212.pdf
(114 pages)
Specifications of LPC1112FHI33/202,5
Core
ARM Cortex M0
Processor Series
LPC1112
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
16 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Factory Pack Quantity
490
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NXP Semiconductors
LPC111X
Product data sheet
7.8.1 Features
7.9.1 Features
7.8 UART
7.9 SPI serial I/O controller
The LPC1110/11/12/13/14/15 contain one UART.
Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode.
The UART includes a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
The LPC1100 and LPC1100L series contain two SPI controllers on the LQFP48 package
and one SPI controller on the HVQFN33/TSSOP28/DIP28/TSSOP20/SO20 packages
(SPI0).
The LPC1100XL series contain two SPI controllers.
Both SPI controllers support SSP features.
The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. The SPI supports full
duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. In practice, often only one of these data flows
carries meaningful data.
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On the LPC1100L and LPC1100XL series, all GPIO pins (except PIO0_4 and PIO0_5)
are pulled up to 3.3 V (V
IOCONFIG block.
Programmable open-drain mode for series LPC1100L and LPC1100XL.
Maximum UART data bit rate of 3.125 MBit/s.
16 Byte Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
FIFO control mechanism that enables software flow control implementation.
Support for RS-485/9-bit mode.
Support for modem control.
Maximum SPI speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
Synchronous serial communication
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 20 February 2013
DD
= 3.3 V) if their pull-up resistor is enabled in the
LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
© NXP B.V. 2013. All rights reserved.
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