MK22DX128VMC5 Freescale Semiconductor, MK22DX128VMC5 Datasheet - Page 47

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MK22DX128VMC5

Manufacturer Part Number
MK22DX128VMC5
Description
ARM Microcontrollers - MCU ARM+128KB +USB
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK22DX128VMC5

Rohs
yes
Core
ARM Cortex M4
Processor Series
K20
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
128 KB
Data Ram Size
32 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
MAPBGA-121
Mounting Style
SMD/SMT
A/d Bit Size
16 bit
Interface Type
I2C, I2S, SPI, UART, USB
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
16
Number Of Timers
4
On-chip Dac
Yes
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
1.71 V
Freescale Semiconductor, Inc.
VLPR (Very Low
VLPS (Very Low
Power Stop)-via
Leakage Stop)
Wait) -via WFI
Low Leakage
Low Leakage
Low Leakage
Low Leakage
VLLS3 (Very
VLLS2 (Very
VLLS1 (Very
VLLS0 (Very
VLPW (Very
Power Run)
Chip mode
Low Power
LLS (Low
Stop 0)
Stop3)
Stop2)
Stop1)
WFI
On-chip voltage regulator is in a low power mode that supplies only
enough power to run the chip at a reduced frequency. Reduced
frequency Flash access mode (1 MHz); LVD off; internal oscillator
provides a low power 4 MHz source for the core, the bus and the
peripheral clocks.
Same as VLPR but with the core in sleep mode to further reduce
power; NVIC remains sensitive to interrupts (FCLK = ON). On-chip
voltage regulator is in a low power mode that supplies only enough
power to run the chip at a reduced frequency.
Places chip in static state with LVD operation off. Lowest power mode
with ADC and pin interrupts functional. Peripheral clocks are stopped,
but LPTimer, RTC, CMP, DAC can be used. NVIC is disabled (FCLK =
OFF); AWIC is used to wake up from interrupt. On-chip voltage
regulator is in a low power mode that supplies only enough power to
run the chip at a reduced frequency. All SRAM is operating (content
retained and I/O states held).
State retention power mode. Most peripherals are in state retention
mode (with clocks stopped), but LLWU, LPTimer, RTC, CMP, DAC can
be used. NVIC is disabled; LLWU is used to wake up.
NOTE: The LLWU interrupt must not be masked by the interrupt
All SRAM is operating (content retained and I/O states held).
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is
used to wake up.
SRAM_U and SRAM_L remain powered on (content retained and I/O
states held).
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is
used to wake up.
SRAM_L is powered off. A portion of SRAM_U remains powered on
(content retained and I/O states held).
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is
used to wake up.
All of SRAM_U and SRAM_L are powered off. The 32-byte system
register file and the 32-byte VBAT register file remain powered for
customer-critical data.
Most peripherals are disabled (with clocks stopped), but LLWU and
RTC can be used. NVIC is disabled; LLWU is used to wake up.
All of SRAM_U and SRAM_L are powered off. The 32-byte system
register file and the 32-byte VBAT register file remain powered for
customer-critical data.
The POR detect circuit can be optionally powered off.
Description
controller to avoid a scenario where the system does not fully
exit stop mode on an LLS recovery.
Table 10. Chip power modes (continued)
K20 Family Product Brief, Rev. 11, 08/2012
Table continues on the next page...
Sleep Deep
Sleep Deep
Sleep Deep
Sleep Deep
Sleep Deep
Sleep Deep
Core mode
Sleep
Run
Wakeup Reset
Wakeup Reset
Wakeup Reset
Wakeup Reset
Power modes
Interrupt
recovery
Interrupt
Interrupt
Interrupt
Wakeup
method
Normal
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