Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 150

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Z8F041APH020SG2156

Manufacturer Part Number
Z8F041APH020SG2156
Description
8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
Manufacturer
ZiLOG
Datasheet

Specifications of Z8F041APH020SG2156

Rohs
yes
Core
eZ8
Processor Series
Z8F041xx
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
4 KB
Data Ram Size
1 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
PDIP-20
Mounting Style
Through Hole
A/d Bit Size
10 bit
A/d Channels Available
8
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
®
Z8 Encore! XP
F082A Series
Product Specification
133
Output Data
The output format of the corrected ADC value is shown below.
MSB
LSB
s v b a 9 8 7 6 5 4 3 2 1 0 – –
The overflow bit in the corrected output indicates that the computed value was greater
than the maximum logical value (+1023) or less than the minimum logical value (–1024).
Unlike the hardware overflow bit, this is not a simple binary flag. For a normal (nonover-
flow) sample, the sign and the overflow bit match. If the sign bit and overflow bit do not
match, a computational overflow has occurred.
Input Buffer Stage
Many applications require the measurement of an input voltage source with a high output
impedance. This ADC provides a buffered input for such situations. The drawback of the
buffered input is a limitation of the input range. When using unity gain buffered mode, the
input signal must be prevented from coming too close to either V
or V
. See
Table 139
SS
DD
on page 236 for details.
This condition applies only to the input voltage level (with respect to ground) of each dif-
ferential input signal. The actual differential input voltage magnitude may be less than
300 mV.
The input range of the unbuffered ADC swings from V
to V
. Input signals smaller
SS
DD
than 300 mV must use the unbuffered input mode. If these signals do not contain low out-
put impedances, they might require off-chip buffering.
Signals outside the allowable input range can be used without instability or device dam-
age. Any ADC readings made outside the input range are subject to greater inaccuracy
than specified.
ADC Control Register Definitions
This section defines the features of the following ADC Control registers.
ADC Control Register 0
(ADCCTL0): see page 134
ADC Control/Status Register 1
(ADCCTL1): see page 136
ADC Data High Byte Register
(ADCD_H): see page 137
ADC Data Low Byte Register
(ADCD_L): see page 137
PS022827-1212
P R E L I M I N A R Y
ADC Control Register Definitions

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