Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 156

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

Low Power Operational Amplifier
PS022827-1212
Operation
Caution:
The LPO is a general-purpose low power operational amplifier. Each of the three ports of
the amplifier is accessible from the package pins. The LPO contains only one pin configu-
ration: ANA0 is the output/feedback node, ANA1 is the inverting input and ANA2 is the
noninverting input.
To use the LPO, it must be enabled in the
state of the LPO is OFF. To use the LPO, the LPO bit must be cleared by turning it ON (for
details, see the
measurements on ANA0 (i.e., measurements not involving the LPO output), the LPO bit
must be turned OFF. Turning the LPO bit ON interferes with normal ADC measurements.
As with other ADC measurements, any pins used for analog purposes must be configured
as such in the GPIO registers. See the
on page 47 for details.
LPO output measurements are made on ANA0, as selected by the
ADC Control Register 0. It is also possible to make single-ended measurements on ANA1
and ANA2 while the amplifier is enabled, which is often useful for determining offset con-
ditions. Differential measurements between ANA0 and ANA2 may be useful for noise
cancellation purposes.
If the LPO output is routed to the ADC, then the
tus Register 1 must also be configured for unity-gain buffered operation. Sampling the
LPO in an unbuffered mode is not recommended.
When either input is overdriven, the amplifier output saturates at the positive or negative
supply voltage. No instability results.
The LPO bit enables the amplifier even in STOP Mode. If the amplifier is not required in
STOP Mode, disable it. Failing to perform this results in STOP Mode currents higher
than necessary.
Power Control Register 0
P R E L I M I N A R Y
Port A–D Alternate Function Subregisters
section on page 33). When making normal ADC
Power Control Register 0 (PWRCTL0)
BUFFMODE
Z8 Encore! XP
Low Power Operational Amplifier
[2:0] bits of ADC Control/Sta-
Product Specification
ANAIN[3:0]
®
. The default
F082A Series
bits of
section
139