Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 40

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
Reset Type
System Reset
System Reset with Crystal
Oscillator Enabled
Stop Mode Recovery
Stop Mode Recovery with
Crystal Oscillator Enabled
Table 8. Reset and Stop Mode Recovery Characteristics and Latency
During a System Reset or Stop Mode Recovery, the Internal Precision Oscillator requires
4
cycles of the Internal Precision Oscillator. If the crystal oscillator is enabled in the Flash
option bits, this reset period is increased to 5000 IPO cycles. When a reset occurs because
of a low voltage condition or Power-On Reset (POR), this delay is measured from the time
that the supply voltage first exceeds the POR level. If the external pin reset remains
asserted at the end of the reset period, the device remains in reset until the pin is deas-
serted.
At the beginning of Reset, all GPIO pins are configured as inputs with pull-up resistor dis-
abled, except PD0 (or PA2 on 8-pin devices) which is shared with the reset pin. On reset,
the PD0 is configured as a bidirectional open-drain reset. The pin is internally driven low
during port reset, after which the user code may reconfigure this pin as a general purpose
output.
During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watchdog Timer oscillator continue to run.
Upon Reset, control registers within the Register File that have a defined Reset value are
loaded with their reset values. Other control registers (including the Stack Pointer, Regis-
ter Pointer and Flags) and general-purpose RAM are undefined following Reset. The eZ8
CPU fetches the Reset vector at Program Memory addresses
that value into the Program Counter. Program execution begins at the Reset vector
address.
As the control registers are reinitialized by a system reset, the system clock after reset is
always the IPO. The software must reconfigure the oscillator control block, such that the
correct system clock source is enabled and selected.
µ
s to start up. Then the Z8 Encore! XP F082A Series device is held in Reset for 66
Control Registers
Reset (as applicable)
Reset (as applicable)
Unaffected, except
WDT_CTL and
OSC_CTL registers
Unaffected, except
WDT_CTL and
OSC_CTL registers
P R E L I M I N A R Y
Reset Characteristics and Latency
Reset 66 Internal Precision Oscillator Cycles
Reset 5000 Internal Precision Oscillator Cycles
Reset 66 Internal Precision Oscillator Cycles
Reset 5000 Internal Precision Oscillator Cycles
CPU
eZ8
Reset Latency (Delay)
+ IPO startup time
Z8 Encore! XP
0002H
Product Specification
and
®
0003H
F082A Series
Reset Types
and loads
23