Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 46

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
Low Voltage Detection
Reset Register Definitions
Stop Mode Recovery Using the External RESET Pin
When the Z8 Encore! XP F082A Series device is in STOP Mode and the external RESET
pin is driven Low, a system reset occurs. Because of a glitch filter operating on the RESET
pin, the Low pulse must be greater than the minimum width specified, or it is ignored. See
the
In addition to the Voltage Brown-Out (VBO) Reset described above, it is also possible to
generate an interrupt when the supply voltage drops below a user-selected value. For
details about configuring the Low Voltage Detection (LVD) and the threshold levels avail-
able, see the
function is available on the 8-pin product versions only.
When the supply voltage drops below the LVD threshold, the LVD bit of the Reset Status
(RSTSTAT) Register is set to one. This bit remains one until the low-voltage condition
goes away. Reading or writing this bit does not clear it. The LVD circuit can also generate
an interrupt when so enabled, see the
The LVD bit is not latched; therefore, enabling the interrupt is the only way to guarantee
detection of a transient low voltage event.
The LVD functionality depends on circuitry shared with the VBO block; therefore, dis-
abling the VBO also disables the LVD.
The following sections define the Reset registers.
Reset Status Register
The read-only Reset Status (RSTSTAT) Register, shown in Table 11, indicates the source
of the most recent Reset event, indicates a Stop Mode Recovery event and indicates a
Watchdog Timer time-out. Reading this register resets the upper four bits to 0. This regis-
ter shares its address with the write-only Watchdog Timer Control Register.
Table 12 lists the bit settings for Reset and Stop Mode Recovery events.
without initiating an interrupt (if enabled for that pin).
Electrical Characteristics
Trim Option Bits at Address 0003H (TLVD) Register
P R E L I M I N A R Y
chapter on page 226 for details.
GPIO Mode Interrupt Controller
Z8 Encore! XP
Product Specification
on page 166. The LVD
Low Voltage Detection
chapter on page 55.
®
F082A Series
29