Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 67

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Z8F041APH020SG2156

Manufacturer Part Number
Z8F041APH020SG2156
Description
8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
Manufacturer
ZiLOG
Datasheet

Specifications of Z8F041APH020SG2156

Rohs
yes
Core
eZ8
Processor Series
Z8F041xx
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
4 KB
Data Ram Size
1 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
PDIP-20
Mounting Style
Through Hole
A/d Bit Size
10 bit
A/d Channels Available
8
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
PS022827-1212
Bit
Field
RESET
R/W
Address
Bit
[7:0]
PPUEx
Note: x indicates the specific GPIO port pin number (7–0).
Note:
Description
Port Pull-up Enabled
0 = The weak pull-up on the port pin is disabled.
1 = The weak pull-up on the port pin is enabled.
PPUE7
R/W
If 06H in Port A
7
Port A–D Pull-up Enable Subregisters
The Port A–D Pull-up Enable Subregister, shown in Table 26, is accessed through the Port
A–D Control Register by writing
the Port A–D Pull-up Enable subregisters enables a weak internal resistive pull-up on the
specified port pins.
Port A–D Alternate Function Set 1 Subregisters
The Port A–D Alternate Function Set1 Subregister, shown in Table 27, is accessed
through the Port A–D Control Register by writing
The Alternate Function Set 1 subregisters selects the alternate function available at a port
pin. Alternate Functions selected by setting or clearing bits of this register are defined in
the
Alternate function selection on port pins must also be enabled as described in the
D Alternate Function Subregisters
GPIO Alternate Functions
Table 26. Port A–D Pull-Up Enable Subregisters (PxPUE)
PPUE6
R/W
6
00H (Ports A-C); 01H (Port D); 04H (Port A of 8-pin device)
D Address Register, accessible through the Port A
PPUE5
R/W
5
P R E L I M I N A R Y
section on page 37.
PPUE4
06H
R/W
section on page 47.
4
to the Port A–D Address Register. Setting the bits in
PPUE3
R/W
3
07H
Z8 Encore! XP
to the Port A–D Address Register.
GPIO Control Register Definitions
PPUE2
R/W
2
Product Specification
D Control Register
PPUE1
R/W
1
®
F082A Series
PPUE0
Port A–
R/W
0
50

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