Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 94

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
The PWM period is represented by the following equation:
If an initial starting value other than
registers, use the ONE-SHOT Mode equation to determine the first PWM time-out period.
If TPOL is set to 0, the ratio of the PWM output High time to the total period is repre-
sented by:
PWM Output High Time Ratio (%)
If TPOL is set to 1, the ratio of the PWM output High time to the total period is repre-
sented by:
PWM DUAL OUTPUT Mode
In PWM DUAL OUTPUT Mode, the timer outputs a Pulse-Width Modulated (PWM) out-
put signal pair (basic PWM signal and its complement) through two GPIO port pins. The
timer input is the system clock. The timer first counts up to the 16-bit PWM match value
stored in the Timer PWM High and Low Byte registers. When the timer count value
matches the PWM value, the Timer Output toggles. The timer continues counting until it
reaches the reload value stored in the Timer Reload High and Low Byte registers. Upon
reaching the reload value, the timer generates an interrupt, the count value in the Timer
High and Low Byte registers is reset to
If the TPOL bit in the Timer Control Register is set to 1, the Timer Output signal begins as
a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The
Timer Output signal returns to a High (1) after the timer reaches the reload value and is
reset to
If the TPOL bit in the Timer Control Register is set to 0, the Timer Output signal begins as
a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The
Timer Output signal returns to a Low (0) after the timer reaches the reload value and is
reset to
The timer also generates a second PWM output signal Timer Output Complement. The
Timer Output Complement is the complement of the Timer Output PWM signal. A pro-
grammable deadband delay can be configured to time delay (0 to 128 system clock cycles)
PWM output transitions on these two pins from a low to a high (inactive to active). This
PWM Period (s)
PWM Output High Time Ratio (%)
0001H
0001H
.
.
=
----------------------------------------------------------------------- -
System Clock Frequency (Hz)
Reload Value Prescale
P R E L I M I N A R Y
=
=
0001H

Reload Value PWM Value
----------------------------------------------------------------- -
--------------------------------
Reload Value
PWM Value
0001H
is loaded into the Timer High and Low Byte
Reload Value
and counting resumes.
–

100
Z8 Encore! XP
Product Specification

100
®
F082A Series
Operation
77