Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 97

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
5. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing
6. Configure the associated GPIO port pin for the Timer Input alternate function.
7. Write to the Timer Control Register to enable the timer and initiate counting.
In CAPTURE Mode, the elapsed time from timer start to Capture event can be calculated
using the following equation:
CAPTURE RESTART Mode
In CAPTURE RESTART Mode, the current timer count value is recorded when the
acceptable external Timer Input transition occurs. The Capture count value is written to
the Timer PWM High and Low Byte registers. The timer input is the system clock. The
TPOL bit in the Timer Control Register determines if the Capture occurs on a rising edge
or a falling edge of the Timer Input signal. When the Capture event occurs, an interrupt is
generated and the count value in the Timer High and Low Byte registers is reset to
and counting resumes. The INPCAP bit in TxCTL0 Register is set to indicate the timer
interrupt is because of an input capture event.
If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer
generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
0001H
the timer interrupt is not caused by an input capture event.
Observe the following steps for configuring a timer for CAPTURE RESTART Mode and
initiating the count:
1. Write to the Timer Control Register to:
2. Write to the Timer High and Low Byte registers to set the starting count value (typi-
Capture Elapsed Time (s)
to the relevant interrupt registers. By default, the timer interrupt is generated for both
input capture and reload events. If appropriate, configure the timer interrupt to be gen-
erated only at the input capture event or the reload event by setting TICONFIG field
of the TxCTL0 Register.
–
–
–
–
cally
and counting resumes. The INPCAP bit in TxCTL0 Register is cleared to indicate
Disable the timer
Configure the timer for CAPTURE RESTART Mode by writing the TMODE bits
in the TxCTL1 Register and the
Set the prescale value
Set the Capture edge (rising or falling) for the Timer Input
0001H
).
P R E L I M I N A R Y
=

-------------------------------------------------------------------------------------------------- -
Capture Value
System Clock Frequency (Hz)
TMODEHI
–
Start Value
bit in TxCTL0 Register
Z8 Encore! XP


Prescale
Product Specification
®
F082A Series
Operation
0001H
80