LFE3-95EA-7LFN1156I Lattice, LFE3-95EA-7LFN1156I Datasheet
LFE3-95EA-7LFN1156I
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LFE3-95EA-7LFN1156I Summary of contents
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... LatticeECP3 FPGAs offer up to 150K LUTs of logic capacity and 7 Mbits of memory for system integration, cascadable high- performance DSP blocks for signal processing, high-speed memory interfaces including DDR3 at 800 Mbps, and Gbps LVDS performance for ADC/DAC and SPI4 ...
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... LatticeECP3 Architecture Architecture Overview LatticeECP3 FPGAs utilize Lattice’s third generation of cost optimized transceivers and a low-power 65-nm process FPGA architecture. Building on the successful LatticeECP2M family, LatticeECP3 devices deliver high-performance SERDES blocks, cascadable high-performance sysDSP and sysMEM embedded RAM, distributed memory, sysCLOCK ™ ...
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... The LatticeECP3 Serial Protocol Board provides a platform to evaluate the LatticeECP3 device's multi-protocol serial protocol functionality as well as DDR2 and DDR3 memory interfaces. The LatticeECP3 Video Protocol Board provides a platform to evaluate the LatticeECP3 device's multi-rate 3G/HD/SDI and 7:1 LVDS capabilities. Breakout options for other display interfaces are also available. ...
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... Copyright © 2012 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), ispLEVER, ispLeverCORE, Lattice Diamond, LatticeCORE, LatticeECP3, LatticeECP2M, LatticeMico32, sysCLOCK, sysCONFIG, sysDSP, sysIO, sysMEM, and TransFR are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ...