LCMXO2-256ZE-2SG32CES Lattice, LCMXO2-256ZE-2SG32CES Datasheet - Page 28
LCMXO2-256ZE-2SG32CES
Manufacturer Part Number
LCMXO2-256ZE-2SG32CES
Description
FPGA - Field Programmable Gate Array 256 LUTs 22 I/O 1.2V engineering sample
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-256ZE-2SG32CES
Rohs
yes
Maximum Operating Frequency
125 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
QFN-32
Minimum Operating Temperature
0 C
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Table 2-12. Supported Input Standards
Types of Output Buffers
Differential Output Emulation
Capability
PCI Clamp Support
Single-Ended Interfaces
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI
SSTL18 (Class I, Class II)
SSTL25 (Class I, Class II)
HSTL18 (Class I, Class II)
Differential Interfaces
LVDS
BLVDS, MVDS, LVPECL, RSDS
Differential SSTL18 Class I, II
Differential SSTL25 Class I, II
Differential HSTL18 Class I, II
1. Bottom banks of MachXO2-640U, MachXO2-1200/U and higher density devices only.
2. Reduced functionality. Refer to TN1202,
1
No
Single-ended buffers with
complementary outputs (all I/O
banks)
All I/O banks
Input Standard
MachXO2-256,
MachXO2-640
MachXO2 sysIO Usage Guide
2-24
Single-ended buffers with
complementary outputs (all I/O
banks)
Differential buffers with true
LVDS outputs (50% on top
side)
All I/O banks
Clamp on bottom side only
3.3V
2
2
2
2
MachXO2-640U,
MachXO2-1200
2.5V
2
2
2
2
2
VCCIO (Typ.)
1.8V
2
2
2
2
2
for more detail.
MachXO2 Family Data Sheet
1.5
2
2
2
2
2
Single-ended buffers with
complementary outputs (all I/O
banks)
Differential buffers with true
LVDS outputs (50% on top
side)
All I/O banks
Clamp on bottom side only
1.2V
MachXO2-2000/U,
MachXO2-1200U
MachXO2-4000,
MachXO2-7000
2
Architecture
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