1893AFLF IDT, 1893AFLF Datasheet

1893AFLF

Manufacturer Part Number

1893AFLF

Description

Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER

Manufacturer

IDT

Type

Integrated PHY Transceiverr

Datasheet

1.1893AFLF.pdf (136 pages)

Specifications of 1893AFLF

Rohs

yes

Product

Ethernet Transceivers

Data Rate

10 Mb/s, 100 Mb/s

Supply Voltage - Max

3.47 V

Supply Voltage - Min

3.14 V

Maximum Operating Temperature

+ 70 C

Package / Case

SSOP-48

Ethernet Connection Type

100Base-TX, 10Base-T

Maximum Supply Current

160 mA

Minimum Operating Temperature

0 C

Standard Supported

802.3

Part # Aliases

ICS1893AFLF

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General

The ICS1893AF is a lower cost, re-packaged version of the

ICS1893Y-10. The ICS1893AF is a fully integrated, Physical

Layer device (PHY) that is compliant with both the 10Base-T

and 100Base-TX CSMA/CD Ethernet Standard, ISO/IEC

8802-3. The ICS1893AF uses the same proven silicon as

the ICS1893Y-10 but offers a lower cost solution by using a

lower cost 300 mil. 48-lead SSOP package.

The ICS1893AF uses the same twisted-pair transmit and

receive circuits as the ICS1893Y-10, and the same

recommended board layout techniques apply to the

ICS1893AF.

The ICS1893AF is intended for Node applications using the

standard MII interface to the MAC.

All differences in the ICS1893AF / ICS1893Y-10 Feature Set

are listed in the Comparison Table on page 14.

ICS1893AF, Rev. F 05/13/10

ICS1893AF Block Diagram

Management

10/100 MII

MII Serial

Interface

MAC

3.3-V 10Base-T/100Base-TX Integrated PHYceiver

Extended

Interface

Integrated Circuit Systems, Inc.

MUX

Set

MII

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any information

being relied upon by the customer is current and accurate.

PCS

•

Synthesizer

ICS1893AF

Low-Jitter

Framer

CRS/COL

Detection

Parallel to Serial

4B/5B

Clock

PMA

•

100Base-T

10Base-T

Power

Clock Recovery

Link Monitor

Signal Detection

Error Detection

Features

•

Single 3.3V power supply

Supports category 5 cables with attenuation in excess of

24dB at 100 MHz.

DSP-based baseline wander correction to virtually

eliminate killer packets

Low-power, 0.35-micron CMOS (typically 400 mW)

Single-chip, fully integrated PHY provides PCS, PMA,

PMD, and AUTONEG sublayers of IEEE standard

10Base-T and 100Base-TX IEEE 802.3 compliant

Clock or crystal supported

Media Independent Interface (MII) supported

Managed or Unmanaged Applications

10M or 100M Half and Full Duplex Modes

Auto-Negotiation with Parallel detection for Legacy

products

Fully integrated, DSP-based PMD includes:

– Adaptive equalization and baseline wander correction

– Transmit wave shaping and stream cipher scrambler

– MLT-3 encoder and NRZ/NRZI encoder

Loopback mode for Diagnostic Functions

Small footprint 48-pin 300 mil SSOP package. Available in

Industrial Temperature and Lead Free packaging.

TP_PMD

•

Configuration

and Status

LEDs and PHY

Address

MLT-3

Stream Cipher

Adaptive Equalizer

Baseline Wander

Correction

Document Type:

Document Stage: Release

Negotiation

Integrated

Switch

Auto-

Data Sheet

Modules and

Interface to

Connector

Magnetics

Twisted-

RJ45

Pair

Octobe

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