73S8010R-IM/F1 Maxim Integrated, 73S8010R-IM/F1 Datasheet
73S8010R-IM/F1
Specifications of 73S8010R-IM/F1
Related parts for 73S8010R-IM/F1
73S8010R-IM/F1 Summary of contents
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... Simplifying System Integration™ DS_8010R_022 DESCRIPTION The Teridian 73S8010R is a single smart card interface IC that provides full electrical compliance with ISO-7816-3 and EMV 4.0 (EMV2000) specifications. Interfacing with the host is done through the two-wire bus and one interrupt output to inform the system controller of the card presence and faults ...
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... VPC FAULT VDD FAULT VCC FAULT Int_Clk R-C OSC DIGITAL & ISO-7816 SEQUENCER CLOCK ICC I/O BUFFERS Pin numbers reference the SO28 package reference the QFN32 Package Figure 1: 73S8010R Block Diagram DS_8010R_022 VPC 5 [3] 6 [1] LDO REGULATOR [12] & VOLTAGE SUPERVISORS [15] ICC RESET [14] BUFFER ...
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... Smart Card Interface Requirements ........................................................................................ 9 2.4 Digital Signals Characteristics ............................................................................................... 11 2.5 DC Characteristics ................................................................................................................ Interface Characteristics .................................................................................................. 12 2.7 Voltage / Temperature Fault Detection Circuits ...................................................................... 12 3 Applications Information ............................................................................................................. 13 3.1 Example 73S8010R Schematics ........................................................................................... 13 3.2 System Controller Interface (I 3.3 Power Supply and Voltage Supervision ................................................................................. 17 3.4 Card Power Supply ............................................................................................................... 18 3.5 Over-temperature Monitor ..................................................................................................... 18 3.6 On-chip Oscillator and Card Clock......................................................................................... 18 3.7 Activation Sequence ............................................................................................................. 19 3.8 Deactivation Sequence ...
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... Data Sheet Figures Figure 1: 73S8010R Block Diagram ......................................................................................................... 2 Figure 2: 73S8010R 32-Pin QFN Pinout .................................................................................................. 5 Figure 3: 73S8010R 28-Pin SO Pinout ..................................................................................................... 5 Figure 4: Typical 73S8010R Application Schematic ............................................................................... 13 2 Figure Bus Write Protocol ............................................................................................................ 15 2 Figure Bus Read Protocol ............................................................................................................ 16 2 Figure Bus Timing Diagram .......................................................................................................... 16 Figure 8: Activation Sequence ............................................................................................................... 19 Figure 9: Deactivation Sequence ...
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... DS_8010R_022 1 Pinout The 73S8010R is supplied as a 32-pin QFN package and as a 28-pin SO package. GND 1 GND 2 VPC PRES 7 I/O 8 Figure 2: 73S8010R 32-Pin QFN Pinout SAD0 SAD1 SAD2 GND GND VPC PRES AUX2 AUX1 GND Rev. 1.6 TERIDIAN 73S8010R ...
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... Power Supply and Ground VDD 21 VPC 6 GND 4 GND 14 GND 5, 22 2,21 6 Table 1: 73S8010R Pin Definitions Pin Type 8 IO Card I/O: Data signal to/from card. Includes a pull-up resistor AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor AUX2: Auxiliary data signal to/from card. Includes a ...
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... System controller auxiliary data I/O to/from the card. Includes an internal pull-up resistor System controller auxiliary data I/O to/from the card. Includes an internal pull-up resistor to V 73S8010R Data Sheet Description is provided bit SAD1 SAD0 Address ...
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... Voltage / Temperature Fault Detection Circuits 2.1 Absolute Maximum Ratings Table 2 lists the maximum operating conditions for the 73S8010R. Permanent device damage may occur if absolute maximum ratings are exceeded. Exposure to the extremes of the absolute maximum rating for extended periods may affect device reliability. ...
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... DS_8010R_022 2.3 Smart Card Interface Requirements Table 4 lists the 73S8010R Smart Card interface requirements. Table 4: DC Smart Card Interface Requirements Symbol Parameter Card Power Supply (V ) Regulator CC General Conditions: -40 °C < T < 85 °C, 4.75 V < V Card supply voltage including ripple and V CC noise I Maximum supply current ...
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... Data Sheet Symbol Parameter Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC and V SHORTL SHORTH V Output level, high (I/O, OH AUX1, AUX2) V Output level, high OH (I/OUC, AUX1UC, AUX2UC) V Output level, low OL V Input level, high (I/O, IH AUX1, AUX2) ...
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... Output current limit, CLK CLK_LIM Output rise time, fall time R F δ Duty cycle for CLK 2.4 Digital Signals Characteristics Table 5 lists the 73S8010R digital signals characteristics. Table 5: Digital Signals Characteristics Symbol Parameter Digital I/O except for OSC I/O V Input low voltage IL V Input high voltage IH ...
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... Data Sheet 2 2 Interface Characteristics 2 Table 7 lists the I C Interface characteristics. Symbol Parameter V Input low voltage IL V Input high voltage IH V Output low voltage OL C Pin capacitance IN I Output high voltage IN T Output fall time F T Pulse width of spikes SP that are suppressed 2 ...
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... This section provides general usage information for the design and implementation of the 73S8010R. 3.1 Example 73S8010R Schematics Figure 4 shows a typical application schematic for the implementation of the 73S8010R. Note that minor changes may occur to the reference material from time to time and the reader is encouraged to contact Teridian for the latest information See note 7 ...
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... A fast-mode 400 kHz I C bus slave interface is used for controlling the 73S8010R device and reading the status of the device via the data pin SDA and clock pin SCL. The bus has 3 address select pins, SAD0, SAD1, and SAD2. This allows devices to be connected in parallel. Table 9 lists the device address selections for the SAD2:0 settings ...
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... The master should send the STOP condition after receiving the ACK bit. Rev. 1.6 LSB MSB 8 9 ACK bit R/W bit 2 Figure Bus Write Protocol Table 12: Status Register Description Power On Reset = 0x04 is on); reset when the card is inactive. CC 73S8010R Data Sheet LSB 9 1-8 STOP DATA bits ACK bit condition 15 ...
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... Data Sheet SDA MSB SCL 1-7 START ADDRESS bits condition SDA SCL Thdsta Symbol Parameter Fsclk Clock frequency Tlow Clock low Thi Clock high Thdsta Hold time START condition Tsudat Data setup time Thddat Data hold time Tsusto Set up time STOP condition ...
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... DS_8010R_022 3.3 Power Supply and Voltage Supervision The Teridian 73S8010R smart card interface IC incorporates a LDO voltage regulator. The voltage output is controlled by the digital input 5V/#V. This regulator is able to provide either card voltage from the power supply applied on the VPC pin. Digital circuitry is powered by the power supply applied on the VDD pin. V range to interface with the system controller ...
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... On-chip Oscillator and Card Clock The Teridian 73S8010R device has an on-chip oscillator that can generate the smart card clock using an external crystal connected between the XTALIN and XTALOUT pins to set the oscillator frequency. When the card clock signal is available from another source, it can be connected to the pin XTALIN, and in this case, the XTALOUT pin should be left unconnected ...
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... Shut down V at the end of time t CC Rev. 1.6 is stable. When Figure 8: Activation Sequence . Out of reception mode 73S8010R Data Sheet has been stable for DD is not valid for any reason, then fault, V fault ...
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... Data Sheet Start/Stop RST CLK IO VCC = > .5 μ > 0.5 μ 3.9 Interrupt The Interrupt is an active low interrupt set low if any of the following internal faults are detected: • V fault CC • V fault DD • V fault PC The interrupt will also be set if one of the following status bit conditions is detected: • ...
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... DS_8010R_022 3.10 Warm Reset The 73S8010R automatically asserts a warm reset to the card when instructed through bit 1 of the I Control register (bit Warm Reset). The warm reset length is automatically defined as 42,000 card clock cycles. The Warm Reset bit is automatically reset when the card starts answering or when the card is declared mute ...
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... Data Sheet 4 Mechanical Drawings 4.1 32-pin QFN TOP VIEW 0.2 MIN. 0.35 / 0.45 Figure 13: 32-pin QFN Package Dimensions 22 0.85 NOM. 2.5 3.0 / 3.75 0.18 / 0.3 1.5 / 1.875 0.25 0.5 BOTTOM VIEW DS_8010R_022 / 0.9MAX. 0.00 / 0.005 0.20 REF. SEATING PLANE SIDE VIEW CHAMFERED 0. Rev. 1.6 ...
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... DS_8010R_022 4.2 28-Pin SO PIN NO. 1 BEVEL .715 (18.161) .695 (17.653) .110 (2.790) .092 (2.336) Figure 14: 28-Pin SO Package Dimensions Rev. 1.6 .050 TYP. (1.270) .305 (7.747) .285 (7.239) .0115 (0.29) .003 (0.076) .016 nom (0.40) 73S8010R Data Sheet .420 (10.668) .390 (9.906) .335 (8.509) .320 (8.128) 23 ...
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... Data Sheet 5 Ordering Information Table 16 lists the order numbers and packaging marks used to identify 73S8010R products. Table 16: Order Numbers and Packaging Marks Part Description 73S8010R–SOL, 28-pin Lead-Free SO 73S8010R–SOL, 28-pin Lead-Free SO Tape / Reel 73S8010R–QFN, 32-pin Lead-Free QFN 73S8010R–QFN, 32-pin Lead-Free QFN Tape / Reel ...
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... Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes no liability for applications assistance. Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com Rev. 1.6 73S8010R Data Sheet Description 25 ...