FT313HL-R FTDI, FT313HL-R Datasheet
FT313HL-R
Specifications of FT313HL-R
Available stocks
Related parts for FT313HL-R
FT313HL-R Summary of contents
Page 1
... SDP, CDP or DCP. Supports VBUS power switching and over current control. -40°C to 85°C extended operating temperature range. Available in compact Pb-free 64 Pin QFN, LQFP and TQFP packages (all RoHS compliant). Document No.: FT_000589 Clearance No.: FTDI# 318 power consumption for portable 1 ...
Page 2
... Printer Instrumentation 1.1 Part Numbers Part Number FT313HQ-x FT313HL-x FT313HP-x Table 1-1 FT313H Numbers Note: Packaging codes for x is: -R: Taped and Reel, (QFN is 3000pcs, LQFP is 1000 pcs, TQFP is 2500pcs per reel) -T: Tray packing, (QFN is 2600pcs, LQFP is 1600 pcs, TQFP is 2500pcs per tray) For example: FT313HQ-R is 3000 QFN pcs in taped and reel packaging 1 ...
Page 3
... Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 DMA RAM 24KB Controller MEMORY ARBITER EHCI Compatible Host Controller ATX OC_N RREF DP DM AGND PSW_N Document No.: FT_000589 Clearance No.: FTDI# 318 VCC(I/O) X1/CLKIN X2 PLL FREQSEL1 FREQSEL2 AGND POR RESET_N GND VCC(1V2) REGULATOR VOUT(1V2) TESTEN ...
Page 4
... USBCMD register (address = 10h) ............................................................................... 22 5.2.5 USBSTS register (address = 14h) ................................................................................ 24 5.2.6 USBINTR register (address = 18h) ............................................................................... 25 5.2.7 FRINDEX register (address = 1Ch) ............................................................................... 26 5.2.8 PERIODICLISTADDR register (address = 24h) ............................................................... 26 5.2.9 ASYNCLISTADDR register (address = 28h) .................................................................... 26 Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Document No.: FT_000589 Clearance No.: FTDI# 318 4 ...
Page 5
... General Multiplex asynchronous bus interface ...................................................... 55 7.1.6 8-Bit General Multiplex asynchronous bus interface ........................................................ 56 8 Package Parameters ................................................................... 57 8.1 QFN-64 Package Dimensions ............................................................ 57 8.2 LQFP-64 Package Dimensions ........................................................... 58 8.3 TQFP-64 Package Dimensions ........................................................... 59 Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Document No.: FT_000589 Clearance No.: FTDI# 318 5 ...
Page 6
... Solder Reflow Profile ........................................................................ 60 9 FTDI Chip Contact Information ................................................... 61 Appendix A – References ........................................................................... 62 Appendix B - List of Figures and Tables ..................................................... 62 Appendix C - Revision History .................................................................... 64 Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Document No.: FT_000589 Clearance No.: FTDI# 318 6 ...
Page 7
... Device Pin Out and Signal Description 3.1 Pin Out – 64pin QFN Figure 3-1 Pin Configuration QFN64 (top-down view) Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Document No.: FT_000589 Clearance No.: FTDI# 318 7 ...
Page 8
... AD8 11 12 AD9 13 AD10 AD11 14 VCC(I/ AD12 Figure 3-2 Pin Configuration LQFP64 (top-down view) Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Document No.: FT_000589 Clearance No.: FTDI# 318 48 PSW_N 47 AGND 46 VOUT(1V2 X1/CLKIN 43 AGND 42 FREQSEL2 41 FREQSEL1 ...
Page 9
... AD8 11 12 AD9 13 AD10 AD11 14 VCC(I/ AD12 Figure 3-3 Pin Configuration TQFP64 (top-down view) Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Document No.: FT_000589 Clearance No.: FTDI# 318 48 PSW_N 47 AGND 46 VOUT(1V2 X1/CLKIN 43 AGND 42 FREQSEL2 41 FREQSEL1 ...
Page 10
... Bidirectional pad; push-pull, three-state output. 3.3V tolerant Bit 10 of the address and data bus I/O Bidirectional pad; push-pull, three-state output. 3.3V tolerant Bit 11 of the address and data bus I/O Bidirectional pad; push-pull, three-state output. 3.3V tolerant I/O supply voltage; connect a 0.1uF decoupling P capacitor Document No.: FT_000589 Clearance No.: FTDI# 318 Description 10 ...
Page 11
... Bit 1 of the address bus; when not in use, connect to GND I Input; 3.3V tolerant Bit 2 of the address bus; when not in use, connect to GND I Input; 3.3V tolerant Bit 3 of the address bus; when not in use, connect to GND I Input; 3.3V tolerant Document No.: FT_000589 Clearance No.: FTDI# 318 Description 11 ...
Page 12
... Input; 3.3V tolerant Input clock frequency selection pin2 I Input; 3.3V tolerant P Analog Ground Crystal oscillator or clock input; 3.3V peak input AI allowed Crystal oscillator output; leave open if an external AO clock is applied on pin X1/CLKIN AO Internal 1.2V regulator output; connect 4.7uF and Document No.: FT_000589 Clearance No.: FTDI# 318 Description 12 ...
Page 13
... Bit 0 to select charging port emulation type Enable test mode. Internal pull-down. I For normal operation leave floating. I Bit 1 to select charging port emulation type I/O : Bi-direction Input and Output AI : Analog Input AO : Analog Output AI/O : Analog Input / Output Document No.: FT_000589 Clearance No.: FTDI# 318 Description 13 ...
Page 14
... LOW 0 HIGH 1 Document No.: FT_000589 Clearance No.: FTDI# 318 Signal Description A[7:0]: 8-bit address bus AD[7:0]: 8-bit data bus Write (WR_N), read (RD_N), chip select (CS_N): control signals for normal SRAM mode DACK: DMA acknowledge input DREQ: DMA request output ...
Page 15
... I WR_N/WE_N I INT O DREQ O DACK I Document No.: FT_000589 Clearance No.: FTDI# 318 Signal Description select: control signals DACK: DMA acknowledge input DREQ: DMA request output AD[15:0]: 16-bit data bus ALE, write(WR_N), read(RD_N), chip select: control signals DACK: DMA acknowledge input DREQ: DMA request output Description ...
Page 16
... ALE/ADV_N and CLE are ignored in a DMA access cycle. Correct data will be captured only on the rising edge of WR_N/WE_N and RD_N /RE_N/OE_N. Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Document No.: FT_000589 Clearance No.: FTDI# 318 16 ...
Page 17
... The frequency selection can be done using the FREQSEL1 and FREQSEL2 pins. Table 4.3 provides clock frequency selection. FREQSEL1 FREQSEL2 Table 4-3 Clock frequency select Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Clock Frequency 12MHz 19.2MHz 24MHz Document No.: FT_000589 Clearance No.: FTDI# 318 17 ...
Page 18
... Clear the U_SUSP_U bit of the EOTTIME register to put the chip into suspend mode. Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Description Supply for digital I/O pad Supply for chip HC_CLK_EN Description 1 Operation mode 0 Suspend mode Document No.: FT_000589 Clearance No.: FTDI# 318 18 ...
Page 19
... FT313H USB2.0 HS Host Controller Datasheet Version 1.1 BCD_EN 1 Standard downstream port, VBUS current limit ≤ 500mA 1 Dedicated charging port, USB host no functional on this port, VBUS current limit ≤ 1.5A 1 Charging downstream port alternative configuration, VBUS current limit ≤ 1. BCD function disable Document No.: FT_000589 Clearance No.: FTDI# 318 Description 19 ...
Page 20
... Memory address register 0000h Data port register 0000h Data session length register 1FA0h Configuration register 0000h Auxiliary memory address register 0000h Auxiliary data port register 0400h Sleep timer register 0000h Host controller interrupt status register Document No.: FT_000589 Clearance No.: FTDI# 318 20 ...
Page 21
... This register is used as an offset added to register base to find out the beginning of the Operational Register Space. Default value Description 28’h0 - Number of Ports 4’h1 This field specifies the number of the physical downstream ports implemented on the host controller. Document No.: FT_000589 Clearance No.: FTDI# 318 21 ...
Page 22
... The only valid values are described as below: Value Max Interrupt Interval for the high-speed 00h Reserved 01h No limited interval 02h 2 micro-frames 04h 4 micro-frames 08h 8 micro-frames (Default, equals to 1 ms) 10h 16 micro-frames (2 ms) 20h 32 micro-frames (4 ms) 40h 64 micro-frames (8 ms) Document No.: FT_000589 Clearance No.: FTDI# 318 22 ...
Page 23
... This field specifies the size of the frame list. 00: 1024 elements (4096 bytes; default value) 01: 512 elements (2048 bytes) 10: 256 elements (1024 bytes) 11: Reserved Host Controller Reset 1’b0 This control bit is used by the software to reset the host controller. Document No.: FT_000589 Clearance No.: FTDI# 318 23 ...
Page 24
... Frame List Index rolls over from its maximum value to zero. Port Change Detect 1’b0 The host controller sets this bit to ’1’ when any port has a change bit transition from ‘0’ to ‘1.’ In addition, this bit is loaded with the OR of all of Document No.: FT_000589 Clearance No.: FTDI# 318 24 ...
Page 25
... When this bit is set to ‘1,’ and the USBINT bit in the USBSTS register is a set to ‘1’ also, the host controller will issue an interrupt at the next interrupt threshold. If set interrupt threshold to 01h, means that when interrupt event occurred, the INT signal will be toggled at once. Document No.: FT_000589 Clearance No.: FTDI# 318 25 ...
Page 26
... Type Default value Description Current Asynchronous List Address R/W 27’h0 This 32-bit register contains the address of the next asynchronous queue head to be executed. These bits correspond to the memory address signals [31:5]. RO 5’b0 - Document No.: FT_000589 Clearance No.: FTDI# 318 (1024) 12 (512) 11 (256) 10 Reserved 26 ...
Page 27
... Before setting this bit, RUN/STOP bit should be set to ‘0.’ Port Suspend 1’ Port is in the suspend state 0 = Port is not in the suspend state. Document No.: FT_000589 Clearance No.: FTDI# 318 USB state SE0 J-state K-state Undefined 27 ...
Page 28
... Connect Status Change 1’ Change current connect status change. This bit indicates a change has occurred in the current connect status of the port. Current Connect Status 1’ Device is presented on the port device is presented. Document No.: FT_000589 Clearance No.: FTDI# 318 Port State Disable Enable Suspend 28 ...
Page 29
... MHz) = 640 clocks (12 MHz) = 53.3 µs 01b 1400 clocks (30 MHz) = 560 clocks (12 MHz) = 46.6 µs 10b 1200 clocks (30 MHz) = 480 clocks (12 MHz µs 11b 21000 clocks (30 MHz) = 8400 clocks (12 MHz)=700 µs Low-Speed EOF1 Time Document No.: FT_000589 Clearance No.: FTDI# 318 29 ...
Page 30
... RO 32’h03130001 Chip ID Type Default value RO 8’b0 RO 2’b00 R/W 1’b0 R/W 1’b0 R/W 1’b0 Document No.: FT_000589 Clearance No.: FTDI# 318 Description - Host Speed Type Indicate the speed type of attached device 2’b10: HS 2’b00: FS 2’b01: LS 2’b11: Reserved DACK Polarity 0: active LOW 1: active HIGH ...
Page 31
... Number of clocks that an Edge Interrupt must be kept asserted on the interface. The default INT pulse width is approximately 500ns. (N+1)*60MHz system clock. Type RO RO Document No.: FT_000589 Clearance No.: FTDI# 318 Description Interrupt Polarity 0: active LOW 1: active HIGH Interrupt Level 0: level trigger 1: Edge trigged. The pulse width depends on the NO_OF_CLK bits in the EDGEINTC register ...
Page 32
... Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Type Default value RO R/W RO R/W R/W R/W Document No.: FT_000589 Clearance No.: FTDI# 318 Description 10b: NOR mode 11b: SRAM mode Write to these bits have no effect. 1’b0 - 1’b0 Data bus width 0: Defines a 16- bit data bus width ...
Page 33
... Type Default value Description R/W 1’b0 BCD Mode override control 0: External CPE0 and CPE1 pins configuration take effect. 1: BCD_MODE [1:0] register bits take effect R/W 2’b00 BCD Mode setting 00: SDP current limit ≥ 500mA. 01: DCP Document No.: FT_000589 Clearance No.: FTDI# 318 Standard downstream port, VBUS 33 ...
Page 34
... R/W 1’b1 BCD module enable 0: disable BCD module 1: enable BCD module RO 1’b0 - R/W 2’b00 DMA burst length 00: Single DMA burst 01: 4-cycle DMA burst 10: 8-cycle DMA burst 11: 16-cycle DMA burst R/W 1’b0 Enable DMA 0: terminate DMA Document No.: FT_000589 Clearance No.: FTDI# 318 34 ...
Page 35
... HCINTEN register is set. Default sleep timer is approximately 10ms. Type Default value Description RO 10’b0 - R/WC 1’b0 Wake up interrupt on device connect or Document No.: FT_000589 Clearance No.: FTDI# 318 Description Auxiliary start address of memory read / write When memory is occurred by DMA, use auxiliary start address for PIO memory access. 35 ...
Page 36
... Indicates the DMA transfer completion. The INT line will be asserted if the respective enable bit in the HCINTEN register is set DMA transfer is completed. 1: DMA transfer is completed. R/WC 1’b0 SOF interrupt The INT line will be asserted if the respective bit enable is set. Document No.: FT_000589 Clearance No.: FTDI# 318 36 ...
Page 37
... USB Bus inactive enable Control the INT generation when the USB bus is inactive 0: No INT will be generated when the USB bus is inactive. 1: INT will be asserted when the USB bus is inactive. R/W 1’b0 Remote wake up interrupt enable Document No.: FT_000589 Clearance No.: FTDI# 318 37 ...
Page 38
... RO 1’b0 - R/W 1’b0 TEST_PACKET After entering the high speed and writing 1’b1 to this bit, users should command the DMA by the test parameter setting registers (0x70h and 0x74h) to move the packet data defined Document No.: FT_000589 Clearance No.: FTDI# 318 38 ...
Page 39
... The transfer type of data moving 0: FIFO to Memory 1: Memory to FIFO DMA Start R/W 1’b0 This bit informs the DMA controller to initiate the DMA transfer. Type Default value Description R/W 32’b0 DMA Memory Address The starting address of memory to request the DMA transfer. Document No.: FT_000589 Clearance No.: FTDI# 318 39 ...
Page 40
... Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Value -65°C to 150°C 168 Hours (IPC/JEDEC J-STD-033A MSL Level 3 Compliant)* -40°C to 85° -0 -0.5 to +5.5 -0 Document No.: FT_000589 Clearance No.: FTDI# 318 Unit Degrees C Hours Degrees ...
Page 41
... Document No.: FT_000589 Clearance No.: FTDI# 318 Units Conditions V V Normal Operation V V Normal Operation mA Idle Normal Operation mA High speed data transfer uA USB suspend V Normal Operation V Normal Operation Units Conditions V Ioh=8mA ...
Page 42
... Document No.: FT_000589 Clearance No.: FTDI# 318 Units Conditions V Ioh=6mA V Iol=6mA Vin = 0 ohm Vin = 0 uA Vin = VCC(I/O) ohm Vin = VCC(I/O) Vin = VCC(I/ Units Conditions V Ioh=3.6mA V Iol=3 ...
Page 43
... Output level for high speed - - -360 - 400 700 - 1100 -900 - -500 0 0.8 - 2.5 0 0.3 2.8 - 3.6 Resistance Document No.: FT_000589 Clearance No.: FTDI# 318 Units Conditions mV - Squelch is mV detected Squelch is not mV detected Disconnection is mV detected Disconnection is mV not detected |Vdp-Vdm ...
Page 44
... VCC(3V3 0.9 - ± ± 2.3 - Value Typical Maximum 12.00 19.20 24. Document No.: FT_000589 Clearance No.: FTDI# 318 Units Conditions Equivalent ohm resistance used as an internal chip Units Conditions V Ioh=2mA~16mA V Iol=2mA~16mA V LVTTL V LVTTL V Ipu = 1uA Vin = VCC(3V3 Vin = VCC(3V3) with 5V pF tolerant I/O Unit ...
Page 45
... Typical Maximum Driver characteristic for high speed 500 - 500 - Driver characteristic for full speed Driver characteristic for low speed Document No.: FT_000589 Clearance No.: FTDI# 318 - V Units Conditions - Cl=50pF 20 ns 10%~90% of |Voh–Vol| Cl=50pF 20 ns 10%~90% of |Voh–Vol| The first transition 110 % ...
Page 46
... Max Min Max 79.5 - Document No.: FT_000589 Clearance No.: FTDI# 318 VCC(I/O)=3.3V Unit Min Max 78 ...
Page 47
... Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Toe Tdadvh Data Tasrw Tahrw Address Trp Tcs Tcp Trc Tdadvh Data Tasrw Tahrw Address Twp Tcs Tcp Twc Document No.: FT_000589 Clearance No.: FTDI# 318 Tdh Tch Tdh Tch 47 ...
Page 48
... VCC(I/O)=2.5V Min Max Min Max 6 Document No.: FT_000589 Clearance No.: FTDI# 318 VCC(I/O)=3.3V Unit Min Max 78 ...
Page 49
... Figure 6-4 Write in NOR mode Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Tah Toe Tbds Tap Trc Tah Tbds Tap Twc Document No.: FT_000589 Clearance No.: FTDI# 318 Tdh Data Trp Tch Tdadvh Tdh Data Tch Twp 49 ...
Page 50
... FT313H USB2.0 HS Host Controller Datasheet Version 1.1 VCC(I/O)=1.8V VCC(I/O)=2.5V Min Max Min Max 7 Document No.: FT_000589 Clearance No.: FTDI# 318 VCC(I/O)=3.3V Unit Min Max ...
Page 51
... Figure 6-6 Write in General Multiplex mode Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Tah Toe Tbds Trc Tah Tbds Tap Twc Document No.: FT_000589 Clearance No.: FTDI# 318 Tdh Data Trp Tch Tdadvh Tdh Data Tch Twp 51 ...
Page 52
... FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Description Assertion Assertion Time Assertion RD_N/WR_N Pulse Width asserts assertion De-assertion DACK Set-up Time before RD_N/WR_N Assertion De-assertion DMA Read/Write Cycle Time Tcyc Trdh Twdh DATA2 Document No.: FT_000589 Clearance No.: FTDI# 318 Min Max Unit - ...
Page 53
... FT313H can be configured to communicate with a microcontroller uses 16-bit/8-bit SRAM asynchronous bus interface, NOR interface, and General Multiplex interface. An example schematic is show in Figure 7.1. Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Document No.: FT_000589 Clearance No.: FTDI# 318 53 ...
Page 54
... If DMA transfers are not used the DACK and DREQ signals may be left floating or the DACK signal may be terminated with external 10k ohm pull-down resistor. Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Microcontroller CS_N RD_N WR_N AD<15:0> A<7:0> INT DACK DREQ Microcontroller CS_N RD_N WR_N AD<7:0> A<7:0> INT DACK DREQ Document No.: FT_000589 Clearance No.: FTDI# 318 54 ...
Page 55
... Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Microcontroller CS_N OE_N WE_N AD<15:0> INT ADV_N Microcontroller CS_N OE_N WE_N AD<7:0> INT ADV_N Microcontroller CS_N RE_N WE_N AD<15:0> INT ALE DACK DREQ Document No.: FT_000589 Clearance No.: FTDI# 318 55 ...
Page 56
... If DMA transfers are not used the DACK and DREQ signals may be left floating or the DACK signal may be terminated with external 10k ohm pull-down resistor. Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Microcontroller CS_N RE_N WE_N AD<7:0> INT ALE DACK DREQ Document No.: FT_000589 Clearance No.: FTDI# 318 56 ...
Page 57
... Package Parameters The FT313H is available in three different packages. The FT313HQ is the QFN-64 package, the FT313HL is the LQFP-64 package and the FT313HP is the TQFP-64 package. The solder reflow profile for all packages is described in following sections. 8.1 QFN-64 Package Dimensions Figure 8-1 QFN-64 Package Dimensions Copyright © ...
Page 58
... LQFP-64 Package Dimensions Figure 8-2 LQFP-64 Package Dimensions Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Document No.: FT_000589 Clearance No.: FTDI# 318 58 ...
Page 59
... TQFP-64 Package Dimensions Figure 8-3 TQFP-64 Package Dimensions Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Document No.: FT_000589 Clearance No.: FTDI# 318 59 ...
Page 60
... Max. 8 minutes Max. p Document No.: FT_000589 Clearance No.: FTDI# 318 the range Non-Pb Free Solder Process 3°C / Second Max. 100°C 150° 120 seconds 183° ...
Page 61
... FTDI disclaims all liability for system designs and for any applications assistance provided by FTDI. Use of FTDI devices in life support and/or safety applications is entirely at the user’s risk, and the user agrees to defend, indemnify and hold harmless FTDI from any and all damages, claims, suits or expense resulting from such use ...
Page 62
... Table 5-12 EOF time and asynchronous schedule sleep timer register ............................................... 30 Table 5-14 HW mode register ....................................................................................................... 31 Table 5-15 Edge interrupt control register ...................................................................................... 31 Table 5-16 SW reset register ........................................................................................................ 32 Table 5-17 Memory address register ............................................................................................. 33 Table 5-18 Data port register ....................................................................................................... 33 Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Document No.: FT_000589 Clearance No.: FTDI# 318 62 ...
Page 63
... Table 6-7 5V Tolerant Pin (PSW_N, OC_N, VBUS) Characteristics ...................................................... 44 Table 6-8 System clock characteristics .......................................................................................... 45 Table 6-9 Analog I/O pins characteristics ....................................................................................... 45 Table 6-10 SRAM PIO timing ........................................................................................................ 46 Table 6-11 NOR PIO timing .......................................................................................................... 48 Table 6-12 General Multiplex PIO timing ........................................................................................ 50 Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 Document No.: FT_000589 Clearance No.: FTDI# 318 63 ...
Page 64
... Product Page: Document Feedback: Version 1.0 Initial Release Version 1.1 Formatting tidy up Copyright © 2012 Future Technology Devices International Limited FT313H USB2.0 HS Host Controller Datasheet Version 1.1 USB Host IC FT313H FT_000589 FTDI# 318 http://www.ftdichip.com/FTProducts.htm DS_FT313H Document No.: FT_000589 Clearance No.: FTDI# 318 OCT 2012 NOV 2012 64 ...