C8051F544-IMR Silicon Labs, C8051F544-IMR Datasheet
C8051F544-IMR
Specifications of C8051F544-IMR
Related parts for C8051F544-IMR
C8051F544-IMR Summary of contents
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Analog Peripherals - 12-Bit ADC Up to 200 ksps • external single-ended inputs • VREF from on-chip VREF, external pin or V • Internal or external start of conversion source • Built-in temperature sensor • - Two ...
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C8051F54x 2 Rev. 1.1 ...
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Table of Contents 1. System Overview ..................................................................................................... 13 2. Ordering Information ............................................................................................... 16 3. Pin Definitions.......................................................................................................... 18 4. Package Specifications ........................................................................................... 23 4.1. QFP-32 Package Specifications........................................................................ 23 4.2. QFN-32 Package Specifications........................................................................ 25 4.3. QFN-24 Package Specifications........................................................................ 27 5. 12-Bit ADC ...
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C8051F54x 15. Power Management Modes................................................................................. 126 15.1. Idle Mode....................................................................................................... 126 15.2. Stop Mode ..................................................................................................... 127 15.3. Suspend Mode .............................................................................................. 127 16. Reset Sources ...................................................................................................... 129 16.1. Power-On Reset ............................................................................................ 130 16.2. Power-Fail Reset/VDD Monitor ..................................................................... 130 16.3. External Reset ............................................................................................... ...
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Signal Descriptions........................................................................................ 215 22.2. SPI0 Master Mode Operation ........................................................................ 216 22.3. SPI0 Slave Mode Operation .......................................................................... 218 22.4. SPI0 Interrupt Sources .................................................................................. 218 22.5. Serial Clock Phase and Polarity .................................................................... 219 22.6. SPI Special Function Registers ..................................................................... 220 23. ...
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C8051F54x List of Figures Figure 1.1. C8051F540/1/4/5 Block Diagram .......................................................... 14 Figure 1.2. C8051F542/3/6/7 Block Diagram .......................................................... 15 Figure 3.1. QFP-32 Pinout Diagram (Top View) ...................................................... 20 Figure 3.2. QFN-32 Pinout Diagram (Top View) ..................................................... 21 Figure 3.3. QFN-24 Pinout ...
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Figure 17.3. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 145 Figure 18.1. Port I/O Functional Block Diagram .................................................... 147 Figure 18.2. Port I/O Cell Block Diagram .............................................................. 148 Figure 18.3. Peripheral Availability on Port I/O Pins .............................................. 151 Figure ...
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C8051F54x Figure 24.3. PCA Interrupt Block Diagram ............................................................ 252 Figure 24.4. PCA Capture Mode Diagram ............................................................. 254 Figure 24.5. PCA Software Timer Mode Diagram ................................................. 255 Figure 24.6. PCA High-Speed Output Mode Diagram ........................................... 256 Figure 24.7. PCA Frequency Output ...
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List of Tables Table 2.1. Product Selection Guide ......................................................................... 17 Table 3.1. Pin Definitions for the C8051F54x .......................................................... 18 Table 4.1. QFP-32 Package Dimensions ................................................................ 23 Table 4.2. QFP-32 Landing Diagram Dimensions ................................................... 24 Table 4.3. QFN-32 Package Dimensions ................................................................ ...
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C8051F54x List of Registers SFR Definition 5.4. ADC0CF: ADC0 Configuration ...................................................... 40 SFR Definition 5.5. ADC0H: ADC0 Data Word MSB .................................................... 41 SFR Definition 5.6. ADC0L: ADC0 Data Word LSB ...................................................... 41 SFR Definition 5.7. ADC0CN: ADC0 Control ................................................................ 42 ...
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SFR Definition 16.1. VDM0CN: VDD Monitor Control ................................................ 132 SFR Definition 16.2. RSTSRC: Reset Source ............................................................ 134 SFR Definition 17.1. CLKSEL: Clock Select ............................................................... 136 SFR Definition 17.2. OSCICN: Internal Oscillator Control .......................................... 138 SFR Definition 17.3. OSCICRS: Internal Oscillator ...
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C8051F54x SFR Definition 21.6. SBRLL0: UART0 Baud Rate Generator Reload Low Byte ........ 213 SFR Definition 21.5. SBRLH0: UART0 Baud Rate Generator Reload High Byte ....... 213 SFR Definition 22.1. SPI0CFG: SPI0 Configuration ................................................... 221 SFR Definition 22.2. SPI0CN: SPI0 ...
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... The oscillator is within +1.0% for VDD voltages below this minimum output setting. On-chip Clock Multiplier to reach MHz (C8051F540/1/2/ (C8051F544/5/6/7) of on-chip Flash memory 1280 bytes of on-chip RAM SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware ...
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C8051F54x Power On CIP-51 8051 Controller Reset Core (50 MHz) Reset 16 kB Flash Program Memory Debug / C2CK/RST Programming 256 Byte RAM Hardware C2D 1 kB XRAM Voltage Regulator VREGIN (LDO) VDD GND System Clock Setup XTAL1 Internal Oscillator ...
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Power On CIP-51 8051 Controller Reset Core (50 MHz) Reset 16 kB Flash Program Memory C2CK/RST Debug / Programming 256 Byte RAM Hardware C2D 1 kB XRAM Voltage Regulator VREGIN (LDO) VDD GND System Clock Setup XTAL1 XTAL2 Internal Oscillator ...
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C8051F54x 2. Ordering Information The following features are common to all devices in this family: 50 MHz system clock and 50 MIPS throughput (peak) 1280 bytes of RAM (256 internal bytes and 1024 XRAM bytes) Internal 24 ...
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... C8051F540-IM C8051F541-IQ C8051F541-IM C8051F542-IM C8051F543-IM C8051F544-IQ C8051F544-IM C8051F545-IQ C8051F545-IM C8051F546-IM C8051F547-IM Note: The suffix of the part number indicates the device rating and the package. All devices are RoHS compliant. All of these devices are also available in an automotive version. For the automotive version, the -I in the ordering part number is replaced with -A ...
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C8051F54x 3. Pin Definitions Table 3.1. Pin Definitions for the C8051F54x Name Pin Pin ‘F540/1/4/5 ‘F542/3/6/7 (32-pin) (24-pin) VDD 4 3 GND 6 4 VDDA 5 — GNDA 7 5 VREGIN 3 2 VIO 2 1 RST C2CK ...
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Table 3.1. Pin Definitions for the C8051F54x (Continued) Name Pin Pin ‘F540/1/4/5 ‘F542/3/6/7 (32-pin) (24-pin Port 1. Port 1.4. P1 I/O ...
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... C8051F54x 1 P0.1 / CNVSTR VIO 2 VREGIN 3 VDD 4 VDDA 5 6 GND 7 GNDA 8 P0.0 / VREF Figure 3.1. QFP-32 Pinout Diagram (Top View) 20 C8051F540-IQ C8051F541-IQ C8051F544-IQ C8051F545-IQ Top View Rev. 1.1 24 P1.2 23 P1.3 22 P1.4 21 P1.5 20 P1.6 19 P1.7 18 P2.0 17 P2.1 ...
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... P0.1 / CNVSTR 1 VIO 2 VREGIN 3 VDD 4 VDDA 5 GND 6 GNDA 7 P0.0 / VREF 8 Figure 3.2. QFN-32 Pinout Diagram (Top View) C8051F540-IM C8051F541-IM C8051F544-IM C8051F545-IM Top View GND Rev. 1.1 C8051F54x 24 P1.2 23 P1.3 22 P1.4 21 P1.5 20 P1.6 19 P1.7 18 P2.0 17 P2.1 21 ...
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C8051F54x VIO 1 VREGIN 2 VDD 3 GND 4 GNDA 5 P0.0/VREF 6 Figure 3.3. QFN-24 Pinout Diagram (Top View) 22 C8051F542-IM C8051F543-IM C8051F546-IM C8051F547-IM Top View GND Rev. 1.1 18 P0.7/CAN0 RX 17 P1.0 16 P1.1 15 P1.2 14 ...
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Package Specifications 4.1. QFP-32 Package Specifications Figure 4.1. QFP-32 Package Drawing Table 4.1. QFP-32 Package Dimensions Dimension Min Typ A — — A1 0.05 — A2 1.35 1.40 b 0.30 0.37 c 0.09 — D 9.00 BSC. D1 7.00 ...
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C8051F54x Figure 4.2. QFP-32 Landing Diagram Table 4.2. QFP-32 Landing Diagram Dimensions Dimension Min C1 8.40 C2 8.40 E 0.80 BSC Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is ...
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QFN-32 Package Specifications Figure 4.3. QFN-32 Package Drawing Table 4.3. QFN-32 Package Dimensions Dimension Min Typ A 0.80 0.9 A1 0.00 0.02 b 0.18 0.25 D 5.00 BSC. D2 3.20 3.30 e 0.50 BSC. E 5.00 BSC. Notes: 1. ...
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C8051F54x Figure 4.4. QFN-32 Landing Diagram Table 4.4. QFN-32 Landing Diagram Dimensions Dimension Min C1 4.80 C2 4.80 e 0.50 BSC X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern ...
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QFN-24 Package Specifications Figure 4.5. QFN-24 Package Drawing Table 4.5. QFN-24 Package Dimensions Dimension Min Typ A 0.70 0.75 A1 0.00 0.02 b 0.18 0.25 D 4.00 BSC D2 2.55 2.70 e 0.50 BSC E 4.00 BSC E2 2.55 ...
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C8051F54x Figure 4.6. QFN-24 Landing Diagram Table 4.6. QFN-24 Landing Diagram Dimensions Dimension Min C1 3.90 C2 3.90 E 0.50 BSC X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land ...
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ADC (ADC0) The ADC0 on the C8051F54x consists of an analog multiplexer (AMUX0) with 25/18 total input selections and a 200 ksps, 12-bit successive-approximation-register (SAR) ADC with integrated track-and-hold, pro- grammable window detector, programmable attenuation (1:2), and hardware ...
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C8051F54x 5.1. Modes of Operation In a typical system, ADC0 is configured using the following steps gain adjustment is required, refer to Section “5.3. Selectable Gain” on page 35. 2. Choose the start of conversion source. 3. ...
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Post-Tracking Mode is selected when AD0TM is set to 01b. A programmable tracking time based on AD0TK is started immediately following the convert start signal. Conversions are started after the pro- grammed tracking time ends. After a conversion is complete, ...
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C8051F54x Convert Start Time F S1 ADC0 State AD0INT Flag Time F S1 ADC0 State Track AD0INT Flag Key F Sn Figure 5.3. 12-Bit ADC Tracking Mode Example 5.1.4. Burst Mode Burst Mode is a power saving feature that allows ...
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Similarly, the Window Comparator will not compare the result to the greater-than and less-than registers until “repeat count” conversions have been accumulated. Note: When using Burst Mode, care must be taken to issue a convert start signal no ...
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C8051F54x 5.2. Output Code Formatting The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code. When the repeat count is set to 1, conversion codes are represented in 12-bit unsigned integer format and the ...
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Figure 5.5. ADC0 Equivalent Input Circuit 5.3. Selectable Gain ADC0 on the C8051F54x family of devices implements a selectable gain adjustment option. By ...
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C8051F54x For example, if ADC0GNH = 0xFC, ADC0GNL = 0x00, and GAINADD = 1, GAIN = 0xFC0 = 4032, and the resulting equation is as follows: 4032 ------------ - GAIN = 4096 The table below equates values in ...
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Setting the Gain Value The three programmable gain registers are accessed indirectly using the ADC0H and ADC0L registers when the GAINEN bit (ADC0CF.0) bit is set. ADC0H acts as the address register, and ADC0L is the data register. The ...
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C8051F54x Gain Register Definition 5.1. ADC0GNH: ADC0 Selectable Gain High Byte Bit 7 6 Name Type 1 1 Reset Indirect Address = 0x04; Bit Name 7:0 GAINH[7:0] ADC0 Gain High Byte. See Section 5.3.1 for details on calculating the value ...
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Gain Register Definition 5.3. ADC0GNA: ADC0 Additional Selectable Gain Bit 7 6 Name Reserved Reserved Reserved W W Type 0 0 Reset Indirect Address = 0x08; Bit Name 7:1 Reserved Must Write 0000000b. 0 GAINADD ADC0 Additional Gain Bit. Setting ...
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C8051F54x SFR Definition 5.4. ADC0CF: ADC0 Configuration Bit 7 6 AD0SC[4:0] Name Type 1 1 Reset SFR Address = 0xBC; SFR Page = 0x00 Bit Name 7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from ...
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SFR Definition 5.5. ADC0H: ADC0 Data Word MSB Bit 7 6 Name Type 0 0 Reset SFR Address = 0xBE; SFR Page = 0x00 Bit Name 7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits. For AD0LJST = 0 and AD0RPT as ...
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C8051F54x SFR Definition 5.7. ADC0CN: ADC0 Control Bit 7 6 AD0EN BURSTEN AD0INT Name R/W R/W Type 0 0 Reset SFR Address = 0xE8; SFR Page = 0x00; Bit-Addressable Bit Name 7 AD0EN ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 ...
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SFR Definition 5.8. ADC0TK: ADC0 Tracking Mode Select Bit 7 6 AD0PWR[3:0] Name R/W Type 1 1 Reset SFR Address = 0xBA; SFR Page = 0x00; Bit Name 7:4 AD0PWR[3:0] ADC0 Burst Power-Up Time. For BURSTEN = 0: ADC0 Power ...
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C8051F54x SFR Definition 5.9. ADC0GTH: ADC0 Greater-Than Data High Byte Bit 7 6 Name Type 1 1 Reset SFR Address = 0xC4; SFR Page = 0x00 Bit Name 7:0 ADC0GTH[7:0] ADC0 Greater-Than Data Word High-Order Bits. SFR Definition 5.10. ADC0GTL: ...
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SFR Definition 5.11. ADC0LTH: ADC0 Less-Than Data High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xC6; SFR Page = 0x00 Bit Name 7:0 ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits. SFR Definition 5.12. ADC0LTL: ADC0 ...
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C8051F54x ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (4095/4096) 0x0FFF not affected 0x0201 VREF x (512/4096) 0x0200 ADC0LTH:ADC0LTL 0x01FF 0x0101 VREF x (256/4096) 0x0100 ADC0GTH:ADC0GTL 0x00FF not affected 0x0000 0 Figure 5.6. ADC Window Compare Example: Right-Justified Data ADC0H:ADC0L ...
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Electrical Characteristics 6.1. Absolute Maximum Specifications Table 6.1. Absolute Maximum Ratings Parameter Ambient Temperature under Bias Storage Temperature Voltage on V with Respect to GND REGIN Voltage on V with Respect to GND DD Voltage on VDDA with Respect ...
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C8051F54x 6.2. Electrical Characteristics Table 6.2. Global Electrical Characteristics –40 to +125 °C, 24 MHz system clock unless otherwise specified. Parameter Supply Input Voltage (V ) REGIN Digital Supply Voltage (V ) System Clock < 25 MHz DD System Clock ...
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Table 6.2. Global Electrical Characteristics (Continued) –40 to +125 °C, 24 MHz system clock unless otherwise specified. Parameter Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash ...
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C8051F54x Figure 6.1. Minimum VDD Monitor Threshold vs. System Clock Frequency Note: With system clock frequencies greater than 25 MHz, the V (VDMLVL = 1b in SFR VDM0CN) to prevent undefined CPU operation. The high threshold should only be used ...
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Table 6.3. Port I/O DC Electrical Characteristics V = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified. DD Parameters Output High Voltage I = –3 mA, Port I/O push-pull –10 µA, Port I/O push-pull ...
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... Monitor Turn-on Time DD V Monitor Supply Current DD Table 6.5. Flash Electrical Characteristics V = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified. DD Parameter Conditions Flash Size C8051F540/1/2/3 C8051F544/5/6/7 Endurance Retention 125 C ° Erase Cycle Time 25 MHz System Clock Write Cycle Time 25 MHz System Clock V Write/Erase Operations DD 1 ...
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Table 6.6. Internal High-Frequency Oscillator Electrical Characteristics V = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified; Using factory-calibrated settings. DD Parameter Oscillator Frequency IFCN = 111b; VDD > VREGMIN IFCN = 111b; VDD < VREGMIN Oscillator ...
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C8051F54x Table 6.7. Clock Multiplier Electrical Specifications V = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified. DD Parameter Input Frequency (Fcm ) in Output Frequency Power Supply Current Table 6.8. Voltage Regulator Electrical Characteristics V = ...
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Table 6.9. ADC0 Electrical Characteristics VDDA = 1.8 to 2.75 V, –40 to +125 °C, VREF = 1.5 V (REFSL=0) unless otherwise specified. Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic 1 Offset Error Full Scale Error Offset ...
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C8051F54x Table 6.10. Temperature Sensor Electrical Characteristics VDDA = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified. Parameter Linearity Slope Slope Error* Offset Offset Error* Power Supply Current Tracking Time *Note: Represents one standard deviation from the ...
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Table 6.12. Comparator 0 and Comparator 1 Electrical Characteristics VIO = 1.8 to 5.25 V, –40 to +125 °C unless otherwise noted. Parameter CPn+ – CPn– = 100 mV Response Time: * Mode 0, Vcm = 1.5 V CPn+ – ...
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C8051F54x 6.1. ADC0 Analog Multiplexer ADC0 includes an analog multiplexer to enable multiple analog input sources. Any of the following may be selected as an input: P0.0–P3.0, the on-chip temperature sensor, the core power supply (V (GND). ADC0 is single-ended ...
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SFR Definition 6.3. ADC0MX: ADC0 Channel Select Bit 7 6 Name Type R R Reset 0 0 SFR Address = 0xBB; SFR Page = 0x00; Bit Name 7:6 Unused Read = 00b; Write = Don’t Care. 5:0 AMX0P[5:0] AMUX0 Positive ...
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C8051F54x 6.2. Temperature Sensor An on-chip temperature sensor is included on the C8051F54x devices which can be directly accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the temperature sensor, the ADC multiplexer channel should ...
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Voltage Reference The Voltage reference multiplexer on the C8051F54x devices is configurable to use an externally con- nected voltage reference, the on-chip reference voltage generator routed to the VREF pin, or the V power supply voltage (see Figure 7.1). ...
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C8051F54x SFR Definition 7.1. REF0CN: Reference Control Bit 7 6 ZTCEN Name R R Type 0 0 Reset SFR Address = 0xD1; SFR Page = 0x00 Bit Name 7:6 Unused Read = 00b; Write = don’t care. 5 ZTCEN Zero ...
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Comparators The C8051F54x devices include two on-chip programmable voltage Comparators. A block diagram of the comparators is shown in Figure 8.1, where “n” is the comparator number (0 or 1). The two Comparators operate identically except that Comparator0 can ...
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C8051F54x Comparator outputs can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system clock; the asynchronous output is ...
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Note that false rising edges and falling edges can be detected when the comparator is first powered changes are made to the hysteresis or response time control bits. Therefore recommended that the rising-edge and falling-edge ...
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C8051F54x SFR Definition 8.2. CPT0MD: Comparator0 Mode Selection Bit 7 6 CP0RIE Name R R Type 0 0 Reset SFR Address = 0x9B; SFR Page = 0x00 Bit Name 7:6 Unused Read = 00b, Write = Don’t Care. 5 CP0RIE ...
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SFR Definition 8.3. CPT1CN: Comparator1 Control Bit 7 6 CP1EN CP1OUT CP1RIF Name R/W R Type 0 0 Reset SFR Address = 0x9D; SFR Page = 0x00 Bit Name 7 CP1EN Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. ...
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C8051F54x SFR Definition 8.4. CPT1MD: Comparator1 Mode Selection Bit 7 6 CP1RIE Name R R Type 0 0 Reset SFR Address = 0x9E; SFR Page = 0x00 Bit Name 7:6 Unused Read = 00b, Write = Don’t Care. 5 CP1RIE ...
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Comparator Multiplexer C8051F54x devices include an analog input multiplexer for each of the comparators to connect Port I/O pins to the comparator inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR Defini- tion 8.5). The CMX0P3–CMX0P0 bits ...
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C8051F54x SFR Definition 8.5. CPT0MX: Comparator0 MUX Selection Bit 7 6 CMX0N[3:0] Name R/W Type 0 1 Reset SFR Address = 0x9C; SFR Page = 0x00 Bit Name 7:4 CMX0N[3:0] Comparator0 Negative Input MUX Selection. 0000: 0001: 0010: 0011: 0100: ...
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SFR Definition 8.6. CPT1MX: Comparator1 MUX Selection Bit 7 6 CMX1N[3:0] Name R/W Type 0 1 Reset SFR Address = 0x9F; SFR Page = 0x00 Bit Name 7:4 CMX1N[3:0] Comparator1 Negative Input MUX Selection. 0000: 0001: 0010: 0011: 0100: 0101: ...
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C8051F54x 9. Voltage Regulator (REG0) C8051F54x devices include an on-chip low dropout voltage regulator (REG0). The input to REG0 at the V pin can be as high as 5.25 V. The output can be selected by software to 2.1 V ...
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V DD 4.7 µF Figure 9.2. External Capacitors for Voltage Regulator Input/Output—Regulator Disabled SFR Definition 9.1. REG0CN: Regulator Control Bit 7 6 REGDIS Reserved Name R/W R/W Type 0 1 Reset SFR Address = 0xC9; SFR Page = 0x00 Bit ...
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C8051F54x 10. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a ...
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... This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or other on-chip resources. C2 details can be found in Section “25. C2 Interface” on page 269. The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro- vides an integrated development environment (IDE) including editor, debugger and programmer. The IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-sys- tem device programming and debugging ...
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C8051F54x 10.2. Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc- tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the ...
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Table 10.1. CIP-51 Instruction Set Summary Mnemonic Arithmetic Operations ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to A ADDC ...
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C8051F54x Table 10.1. CIP-51 Instruction Set Summary (Continued) Mnemonic XRL A, #data Exclusive-OR immediate to A XRL direct, A Exclusive- direct byte XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement A ...
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Table 10.1. CIP-51 Instruction Set Summary (Continued) Mnemonic SETB C Set Carry SETB bit Set direct bit CPL C Complement Carry CPL bit Complement direct bit ANL C, bit AND direct bit to Carry ANL C, /bit AND complement of ...
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C8051F54x Notes on Registers, Operands and Addressing Modes: Rn—Register R0–R7 of the currently selected register bank. @Ri—Data RAM location addressed indirectly through R0 or R1. rel—8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used ...
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SFR Definition 10.1. DPL: Data Pointer Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x82; SFR Page = All Pages Bit Name 7:0 DPL[7:0] Data Pointer Low. The DPL register is the low byte of ...
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C8051F54x SFR Definition 10.3. SP: Stack Pointer Bit 7 6 Name Type 0 0 Reset SFR Address = 0x81; SFR Page = All Pages Bit Name 7:0 SP[7:0] Stack Pointer. The Stack Pointer holds the location of the top of ...
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SFR Definition 10.6. PSW: Program Status Word Bit Name R/W R/W Type 0 0 Reset SFR Address = 0xD0; SFR Page = All Pages; Bit-Addressable Bit Name 7 CY Carry Flag. This bit is set when ...
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C8051F54x 10.4. Serial Number Special Function Registers (SFRs) The C8051F54x devices include four SFRs, SN0 through SN3, that are pre-programmed during production with a unique, 32-bit serial number. The serial number provides a unique identification number for each device and ...
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... C8051F540/1/2/3 RESERVED 0x3C00 0x3BFF 16 kB FLASH (In-System Programmable in 512 Byte Sectors) 0x0000 C8051F544/5/6/7 0x1FFF 8 kB FLASH (In-System Programmable in 512 Byte Sectors) 0x0000 Figure 11.1. C8051F54x Memory Map 11.1. Program Memory The CIP-51 core has program memory space. The C8051F54x devices implement ...
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... SFR space. Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory. Figure 11.1 illustrates the data memory organization of the C8051F54x. 86 0x3FFF 0x3C00 0x3BFF 0x3BFE 0x3A00 C8051F544/5/6/7 Lock Byte Lock Byte Page Flash Memory Space (8 kB Flash Device) 0x0000 Rev. 1.1 0x1FFF ...
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General Purpose Registers The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen- eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these ...
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C8051F54x the DPTR can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and DPL, which contains the lower 8-bits of DPTR. 11.3.2. 8-Bit MOVX Example The 8-bit form of the MOVX instruction uses the ...
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Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the C8051F54x's resources and peripherals. The CIP-51 controller core duplicates the SFRs found ...
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C8051F54x Interrupt Logic CIP-51 Automatic hardware switching of the SFR Page on interrupts may be enabled or disabled as desired using the SFR Automatic Page Control Enable Bit located in the SFR Page Control Register (SFR0CN). This function defaults to ...
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SFR Page Stack Example The following is an example that shows the operation of the SFR Page Stack during interrupts. In this example, the SFR Control register is left in the default enabled state (i.e., SFRPGEN = 1), and ...
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C8051F54x SFRPAGE pushed to SFRNEXT Figure 12.3. SFR Page Stack After SPI0 Interrupt Occurs While in the SPI0 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority interrupt, while the SPI0 interrupt is configured ...
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SFRPAGE pushed to SFRNEXT SFRNEXT pushed to SFRLAST (SMB0ADR) Figure 12.4. SFR Page Stack Upon PCA Interrupt Occurring During a SPI0 ISR On exit from the PCA interrupt service routine, the CIP-51 will return to the SPI0 ISR. On execution ...
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C8051F54x SFRNEXT popped to SFRPAGE SFRLAST popped to SFRNEXT Figure 12.5. SFR Page Stack Upon Return From PCA Interrupt On the execution of the RETI instruction in the SPI0 ISR, the value in SFRPAGE register is overwritten with the contents ...
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SFRNEXT popped to SFRPAGE Figure 12.6. SFR Page Stack Upon Return From SPI0 Interrupt In the example above, all three bytes in the SFR Page Stack are accessible via the SFRPAGE, SFRNEXT, and SFRLAST special ...
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C8051F54x SFR Definition 12.1. SFR0CN: SFR Page Control Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0x84; SFR Page = 0x0F Bit Name 7:1 Unused Read = 0000000b; Write = Don’t Care 0 SFRPGEN SFR ...
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SFR Definition 12.2. SFRPAGE: SFR Page Bit 7 6 Name Type 0 0 Reset SFR Address = 0xA7; SFR Page = All Pages Bit Name 7:0 SFRPAGE[7:0] SFR Page Bits. Represents the SFR Page the C8051 core uses when reading ...
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C8051F54x SFR Definition 12.3. SFRNEXT: SFR Next Bit 7 6 Name Type 0 0 Reset SFR Address = 0x85; SFR Page = All Pages Bit Name 7:0 SFRNEXT[7:0] SFR Page Bits. This is the value that will go to the ...
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SFR Definition 12.4. SFRLAST: SFR Last Bit 7 6 Name Type 0 0 Reset SFR Address = 0xA7; SFR Page = All Pages Bit Name 7:0 SFRLAST[7:0] SFR Page Stack Bits. This is the value that will go to the ...
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C8051F54x Table 12.1. Special Function Register (SFR) Memory Map for Pages 0x0 and 0xF 0(8) 1(9) 2( SPI0CN PCA0L PCA0H F SN0 SN1 P0MAT P0MASK F (All Pages) P0MDIN P1MDIN E8 0 ADC0CN PCA0CPL1 PCA0CPH1 ...
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Table 12.2. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High ADC0GTL 0xC3 ADC0 Greater-Than ...
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C8051F54x Table 12.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address LIN0CF 0xC9 LIN0 Configuration LIN0DAT 0xD2 LIN0 Data OSCICN 0xA1 Internal Oscillator Control OSCICRS 0xA2 Internal Oscillator Coarse Control ...
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Table 12.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address PCA0CPH5 0xCF PCA Capture 5 High PCA0CPL0 0xFB PCA Capture 0 Low PCA0CPL1 0xE9 PCA Capture 1 Low PCA0CPL2 0xEB ...
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C8051F54x Table 12.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address SN0 0xF9 Serial Number 0 SN1 0xFA Serial Number 1 SN2 0xFB Serial Number 2 SN3 0xFC Serial Number ...
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Interrupts The C8051F54x devices include an extended interrupt system supporting a total of 14 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific version of ...
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C8051F54x 13.1.1. Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior- ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot ...
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Table 13.1. Interrupt Summary Interrupt Source Interrupt Vector Reset 0x0000 External Interrupt 0 0x0003 (INT0) Timer 0 Overflow 0x000B External Interrupt 1 0x0013 (INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B ADC0 Window ...
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C8051F54x 13.2. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described in this section. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt ...
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SFR Definition 13.1. IE: Interrupt Enable Bit ESPI0 Name R/W R/W Type 0 0 Reset SFR Address = 0xA8; Bit-Addressable; SFR Page = All Pages Bit Name 7 EA Enable All Interrupts. Globally enables/disables all interrupts. It ...
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C8051F54x SFR Definition 13.2. IP: Interrupt Priority Bit 7 6 PSPI0 Name R R/W Type 1 0 Reset SFR Address = 0xB8; Bit-Addressable; SFR Page = All Pages Bit Name 7 Unused Read = 1b, Write = Don't Care. 6 ...
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SFR Definition 13.3. EIE1: Extended Interrupt Enable 1 Bit 7 6 ELIN0 ET3 Name R/W R/W Type 0 0 Reset SFR Address = 0xE6; SFR Page = All Pages Bit Name 7 ELIN0 Enable LIN0 Interrupt. This bit sets the ...
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C8051F54x SFR Definition 13.4. EIP1: Extended Interrupt Priority 1 Bit 7 6 PLIN0 PT3 Name R/W R/W Type 0 0 Reset SFR Address = 0xF6; SFR Page = 0x00 and 0x0F Bit Name 7 PLIN0 LIN0 Interrupt Priority Control. This ...
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SFR Definition 13.5. EIE2: Extended Interrupt Enable 2 Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xE7; SFR Page = All Pages Bit Name 7:3 Unused Read = 00000b; Write = Don’t Care. 2 EMAT ...
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C8051F54x SFR Definition 13.6. EIP2: Extended Interrupt Priority Enabled 2 Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xF7; SFR Page = 0x00 and 0x0F Bit Name 7:3 Unused Read = 00000b; Write = Don’t ...
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External Interrupts INT0 and INT1 The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active ...
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C8051F54x SFR Definition 13.7. IT01CF: INT0/INT1 Configuration Bit 7 6 IN1PL IN1SL[2:0] Name R/W Type 0 0 Reset SFR Address = 0xE4; SFR Page = 0x0F Bit Name 7 IN1PL INT1 Polarity. 0: INT1 input is active low. 1: INT1 ...
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... The simplest means of programming the Flash memory is through the C2 interface using programming tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initial- ized device. For details on the C2 commands to program Flash memory, see Section “25. C2 Interface” on page 269 ...
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C8051F54x 14.1.3. Flash Write Procedure Flash bytes are programmed by software with the following sequence: 1. Disable interrupts (recommended). 2. Erase the 512-byte Flash page containing the target location, as described in Section 14.1.2. 3. Set the PSWE bit (register ...
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Non-volatile Data Storage The Flash memory can be used for non-volatile data storage as well as program code. This allows data such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX ...
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C8051F54x The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware ...
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Flash Write and Erase Guidelines Any system which contains routines which write or erase Flash memory from software involves some risk that the write or erase routines will execute unintentionally if the CPU is operating outside its specified operating ...
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C8051F54x 14.4.3. System Clock 1. If operating from an external crystal, be advised that crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature. If the system is operating in an electrically noisy ...
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SFR Definition 14.2. FLKEY: Flash Lock and Key Bit 7 6 Name Type 0 0 Reset SFR Address = 0xB7; SFR Page = All Pages Bit Name 7:0 FLKEY[7:0] Flash Lock and Key Register. Write: This register provides a lock ...
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C8051F54x SFR Definition 14.3. FLSCL: Flash Scale Bit 7 6 Name Reserved Reserved Reserved Type R/W R/W Reset 0 0 SFR Address = 0xB6; SFR Page = All Pages Bit Name 7:5 Reserved Must Write 000b. 4 FLRT Flash Read ...
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SFR Definition 14.4. CCH0CN: Cache Control Bit 7 6 Name Reserved Reserved CHPFEN Type R/W R/W Reset 0 0 SFR Address = 0xE3; SFR Page = 0x0F Bit Name 7:6 Reserved Must Write 00b 5 CHPFEN Cache Prefect Enable Bit. ...
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C8051F54x 15. Power Management Modes The C8051F54x devices have three software programmable power management modes: Idle, Stop, and Suspend. Idle mode and Stop mode are part of the standard 8051 architecture, while Suspend mode is an enhanced power-saving mode implemented ...
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Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter Stop mode as soon as the instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripherals ...
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C8051F54x SFR Definition 15.1. PCON: Power Control Bit 7 6 Name Type 0 0 Reset SFR Address = 0x87; SFR Page = All Pages Bit Name 7:2 GF[5:0] General Purpose Flags 5–0. These are general purpose flags for use under ...
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Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: CIP-51 halts program execution Special Function Registers (SFRs) are initialized to their ...
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C8051F54x 16.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until delay occurs before the device is released from reset; the delay decreases as the ...
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... Monitor to the low threshold setting which is guaranteed to be below the un-calibrated DD output of the internal regulator. The device will then exit reset and resume normal operation for this reason Silicon Labs strongly recommends that the V value upon POR). When programming the Flash in-system, the V highest system reliability, the time the V (e ...
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C8051F54x SFR Definition 16.1. VDM0CN: V Bit 7 6 VDMEN VDDSTAT VDMLVL Name R/W R Type Varies Varies Reset SFR Address = 0xFF; SFR Page = 0x00 Bit Name 7 VDMEN V Monitor Enable. DD This bit turns the V ...
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Comparator0 Reset Comparator0 can be configured as a reset source by writing the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on the ...
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C8051F54x SFR Definition 16.2. RSTSRC: Reset Source Bit 7 6 Name FERROR C0RSEF Type R R Reset 0 Varies SFR Address = 0xEF; SFR Page = 0x00 Bit Name Description 7 Unused Unused. 6 FERROR Flash Error Reset Flag. 5 ...
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Oscillators and Clock Selection C8051F54x devices include a programmable internal high-frequency oscillator, an external oscillator drive circuit, and a clock multiplier. The internal oscillator can be enabled/disabled and calibrated using the OSCICN, OSCICRS, and OSCIFIN registers, as shown in ...
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C8051F54x SFR Definition 17.1. CLKSEL: Clock Select Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0x8F; SFR Page = 0x0F; Bit Name 7:2 Unused Read = 000000b; Write = Don’t Care 1:0 CLKSL[1:0] System Clock ...
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Programmable Internal Oscillator All C8051F54x devices include a programmable internal high-frequency oscillator that defaults as the sys- tem clock after a system reset. The internal oscillator period can be adjusted via the OSCICRS and OSCI- FIN registers defined in ...
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C8051F54x SFR Definition 17.2. OSCICN: Internal Oscillator Control Bit 7 6 Name IOSCEN[1:0] SUSPEND Type R/W R/W Reset 1 1 SFR Address = 0xA1; SFR Page = 0x0F; Bit Name 7:6 IOSCEN[1:0] Internal Oscillator Enable Bits. 00: Oscillator Disabled. 01: ...
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SFR Definition 17.3. OSCICRS: Internal Oscillator Coarse Calibration Bit 7 6 Name Type R Reset 0 Varies Varies SFR Address = 0xA2; SFR Page = 0x0F; Bit Name 7 Unused Read = 0; Write = Don’t Care 6:0 OSCICRS[6:0] Internal ...
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C8051F54x 17.3. Clock Multiplier The Clock Multiplier generates an output clock which is 4 times the input clock frequency scaled by a pro- grammable factor of 1, 2/3, 2/4 (or 1/2), 2/5, 2/6 (or 1/3), or 2/7. The Clock Multiplier’s ...
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SFR Definition 17.5. CLKMUL: Clock Multiplier Bit 7 6 Name MULEN MULINIT MULRDY Type R/W R/W Reset 0 0 SFR Address = 0x97; SFR Page = 0x0F; Bit Name 7 MULEN Clock Multiplier Enable. 0: Clock Multiplier disabled. 1: Clock ...
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C8051F54x 17.4. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys- tal/resonator ...
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SFR Definition 17.6. OSCXCN: External Oscillator Control Bit 7 6 Name XTLVLD XOSCMD[2:0] Type R Reset 0 0 SFR Address = 0x9F; SFR Page = 0x0F; Bit Name 7 XTLVLD Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) ...
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C8051F54x 17.4.1. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 17.1, Option 1. The External Oscillator Frequency Control value (XFCN) ...
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Capacitor values depend on crystal specifications Figure 17.3. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 17.4.2. External RC Example network is used as an external oscillator source for the MCU, the circuit ...
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C8051F54x Equation 17.2. C Mode Oscillator Frequency For example: Assume V = 2.1 V and kHz VDD) 0.075 MHz = 2.1) Since the frequency of roughly ...
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Port Input/Output Digital and analog resources are available through 25 (C8051F540/1/4/ (C8051F542/3/6/7) I/O pins. Port pins P0.0-P3.0 on the C8051F540/1/4/5 and port pins P0.0-P2.1 on the C8051F542/3/6/7 can be defined as general-purpose I/O (GPIO), assigned to one ...
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C8051F54x 18.1. Port I/O Modes of Operation Port pins P0.0–P3.0 use the Port I/O cell shown in Figure 18.2. Each Port I/O cell can be configured by software for analog I/O or digital I/O using the PnMDIN registers. On reset, ...
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Interfacing Port I Multi-Voltage System All Port I/O are capable of interfacing to digital logic operating at a supply voltage higher than V than 5.25 V. Connect the V pin to the voltage source of the interface ...
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C8051F54x Table 18.2. Port I/O Assignment for Digital Functions Digital Function Any pin used for GPIO *Note: P2.2-P2.7, P3.0 are only available on the 32-pin packages. 18.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions External digital event ...
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Port P0 Special Function Signals PIN I UART_TX UART_RX SCK MISO MOSI NSS SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 CEX5 ECI T0 T1 LIN_TX LIN_RX Figure 18.3. ...
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C8051F54x Port P0 Special Function Signals PIN I/O UART_TX UART_RX SCK MISO MOSI NSS SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 CEX5 ECI T0 T1 LIN_TX LIN_RX 0 1 ...
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... Crossbar is enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode Table alternative, the Configuration Wizard utility of the Silicon Labs IDE software will deter- mine the Port I/O pin-assignments based on the XBRn Register settings. ...
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C8051F54x SFR Definition 18.1. XBR0: Port I/O Crossbar Register 0 Bit 7 6 Name CP1AE CP1E Type R/W R/W Reset 0 0 SFR Address = 0xE1; SFR Page = 0x0F Bit Name 7 CP1AE Comparator1 Asynchronous Output Enable. 0: Asynchronous ...
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SFR Definition 18.2. XBR1: Port I/O Crossbar Register 1 Bit 7 6 Name T1E T0E Type R/W R/W Reset 0 0 SFR Address = 0xE2; SFR Page = 0x0F Bit Name 7 T1E T1 Enable unavailable at Port ...
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C8051F54x SFR Definition 18.3. XBR2: Port I/O Crossbar Register 1 Bit 7 6 Name WEAKPUD XBARE Type R/W R/W Reset 0 0 SFR Address = 0xC7; SFR Page = 0x0F Bit Name 7 WEAKPUD Port I/O Weak Pullup Disable. 0: ...
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Port Match Port match functionality allows system events to be triggered by a logic value change on P0, P1 P3. A software controlled value stored in the PnMATCH registers specifies the expected or normal logic values of ...
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C8051F54x SFR Definition 18.6. P1MASK: Port 1 Mask Register Bit 7 6 Name Type Reset 0 0 SFR Address = 0xF4; SFR Page = 0x00 Bit Name 7:0 P1MASK[7:0] Port 1 Mask Value. Selects P1 pins to be compared to ...
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SFR Definition 18.8. P2MASK: Port 2 Mask Register Bit 7 6 Name Type Reset 0 0 SFR Address = 0xB2; SFR Page = 0x00 Bit Name 7:0 P2MASK[7:0] Port 2 Mask Value. Selects P2 pins to be compared to the ...
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C8051F54x SFR Definition 18.10. P3MASK: Port 3 Mask Register Bit 7 6 Name 0 0 Type R R Reset 0 0 SFR Address = 0xAF; SFR Page = 0x00 Bit Name 7:1 Unused Read = 0000000b; Write = Don’t Care. ...
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Special Function Registers for Accessing and Configuring Port I/O All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable. When writing to a Port, the value written to the SFR ...
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C8051F54x SFR Definition 18.13. P0MDIN: Port 0 Input Mode Bit 7 6 Name Type Reset 1 1 SFR Address = 0xF1; SFR Page = 0x0F Bit Name 7:0 P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively). Port pins configured for analog ...
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SFR Definition 18.15. P0SKIP: Port 0 Skip Bit 7 6 Name Type Reset 0 0 SFR Address = 0xD4; SFR Page = 0x0F Bit Name 7:0 P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits. These bits select Port 0 pins to ...
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C8051F54x SFR Definition 18.17. P1MDIN: Port 1 Input Mode Bit 7 6 Name Type Reset 1 1 SFR Address = 0xF2; SFR Page = 0x0F Bit Name 7:0 P1MDIN[7:0] Analog Configuration Bits for P1.7–P1.0 (respectively). Port pins configured for analog ...
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SFR Definition 18.19. P1SKIP: Port 1 Skip Bit 7 6 Name Type Reset 0 0 SFR Address = 0xD5; SFR Page = 0x0F Bit Name 7:0 P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits. These bits select Port 1 pins to ...
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C8051F54x SFR Definition 18.21. P2MDIN: Port 2 Input Mode Bit 7 6 Name Type Reset 1 1 SFR Address = 0xF3; SFR Page = 0x0F Bit Name 7:0 P2MDIN[7:0] Analog Configuration Bits for P2.7–P2.0 (respectively). Port pins configured for analog ...
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SFR Definition 18.23. P2SKIP: Port 2 Skip Bit 7 6 Name Type Reset 0 0 SFR Address = 0xD6; SFR Page = 0x0F Bit Name 7:0 P2SKIP[7:0] Port 2 Crossbar Skip Enable Bits. These bits select Port 2 pins to ...
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C8051F54x SFR Definition 18.25. P3MDIN: Port 3 Input Mode Bit 7 6 Name Type R R Reset 1 1 SFR Address = 0xF4; SFR Page = 0x0F Bit Name 7:1 Unused Read = 0000000b; Write = Don’t Care. 0 P3MDIN[0] ...
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SFR Definition 18.27. P3SKIP: Port 3Skip Bit 7 6 Name Type R R Reset 0 0 SFR Address = 0xD7; SFR Page = 0x0F Bit Name 7:1 Unused Read = 0000000b; Write = Don’t Care. 0 P3SKIP[0] Port 3 Crossbar ...
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C8051F54x 19. Local Interconnect Network (LIN) Important Note: This chapter assumes an understanding of the Local Interconnect Network (LIN) proto- col. For more information about the LIN protocol, including specifications, please refer to the LIN consor- tium (http://www.lin-subbus.org). LIN is ...
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Software Interface with the LIN Controller The selection of the mode (Master or Slave) and the automatic baud rate feature are done though the LIN0 Control Mode (LIN0CF) register. The other LIN registers are accessed indirectly through the two ...
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C8051F54x Use the following equations to calculate the values for the variables for the baud-rate equation: prescaler = ln divider = ------------------------------------------------------------------------------------------------------------------------------------- - all of these equations, the results must be rounded down to the nearest integer. ...
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Table 19.2. Manual Baud Rate Parameters Examples 20 K SYSCLK (MHz 312 0 24 306 300 0 22.1184 0 1 276 200 0 12. 306 ...
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C8051F54x Table 19.3. Autobaud Parameters Examples System Clock (MHz) 19.3. LIN Master Mode Operation The master node is responsible for the scheduling of messages and sends the header of each frame con- taining the SYNCH BREAK FIELD, SYNCH FIELD, and ...
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Check the DONE bit (LIN0ST.0) and the ERROR bit (LIN0ST.2 performing a master receive operation and the transfer was successful, read the received data from the data buffer the transfer was not successful, check the ...
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C8051F54x 3. The LIN controller does not directly support LIN Version 1.3 Extended Frames. If the application detects an unknown identifier (e.g. extended identifier), it has to write the STOP bit (LIN0CTRL.7) instead of setting the DTACK ...
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LIN Registers The following Special Function Registers (SFRs) and indirect registers are available for the LIN controller. 19.7.1. LIN Direct Access SFR Registers Definitions SFR Definition 19.1. LIN0ADR: LIN0 Indirect Address Register Bit 7 6 Name Type Reset 0 ...
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C8051F54x SFR Definition 19.3. LIN0CF: LIN0 Control Mode Register Bit 7 6 Name LINEN MODE ABAUD Type R/W R/W R/W Reset 0 1 SFR Address = 0xC9; SFR Page = 0x0F Bit Name 7 LINEN LIN Interface Enable Bit. 0: ...
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LIN Indirect Access SFR Registers Definitions Table 19.4 lists the 15 indirect registers used to configured and communicate with the LIN controller. Table 19.4. LIN Registers* (Indirectly Addressable) Name Address Bit7 LIN0DT1 0x00 LIN0DT2 0x01 LIN0DT3 0x02 LIN0DT4 0x03 ...
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C8051F54x LIN Register Definition 19.4. LIN0DTn: LIN0 Data Byte n Bit 7 6 Name Type Reset 0 0 Indirect Address: LIN0DT1 = 0x00, LIN0DT2 = 0x01, LIN0DT3 = 0x02, LIN0DT4 = 0x03, LIN0DT5 = 0x04, LIN0DT6 = 0x05, LIN0DT7 = ...
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LIN Register Definition 19.5. LIN0CTRL: LIN0 Control Register Bit 7 6 Name STOP SLEEP TXRX Type W R/W Reset 0 0 Indirect Address = 0x08 Bit Name 7 STOP Stop Communication Processing Bit. (slave mode only) This bit always reads ...
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C8051F54x LIN Register Definition 19.6. LIN0ST: LIN0 Status Register Bit 7 6 Name ACTIVE IDLTOUT ABORT Type R R Reset 0 0 Indirect Address = 0x09 Bit Name 7 ACTIVE LIN Active Indicator Bit transmission activity detected on ...
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LIN Register Definition 19.7. LIN0ERR: LIN0 Error Register Bit 7 6 Name Type R R Reset 0 0 Indirect Address = 0x0A Bit Name 7:5 Unused Read = 000b; Write = Don’t Care 4 SYNCH Synchronization Error Bit (slave mode ...
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C8051F54x LIN Register Definition 19.8. LIN0SIZE: LIN0 Message Size Register Bit 7 6 Name ENHCHK Type R/W R Reset 0 0 Indirect Address = 0x0B Bit Name 7 ENHCHK Checksum Selection Bit. 0: Use the classic, specification 1.3 compliant checksum. ...
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LIN Register Definition 19.9. LIN0DIV: LIN0 Divider Register Bit 7 6 Name Type Reset 1 1 Indirect Address = 0x0C Bit Name 7:0 DIVLSB LIN Baud Rate Divider Least Significant Bits. The 8 least significant bits for the baud rate ...
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C8051F54x LIN Register Definition 19.11. LIN0ID: LIN0 Identifier Register Bit 7 6 Name Type R R Reset 0 0 Indirect Address = 0x0E Bit Name 7:6 Unused Read = 00b; Write = Don’t Care. 5:0 ID[5:0] LIN Identifier Bits. These ...
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SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to the interface by the system ...
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C8051F54x 20.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents The I C-Bus and How to Use It (including specifications), Philips Semiconductor The I C-Bus Specification—Version ...
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All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the trans- action is a WRITE operation ...
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C8051F54x overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable and re-enable) the SMBus in the event of an SCL low timeout. 20.3.5. SCL High (SMBus Free) Timeout The SMBus ...
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Table 20.1. SMBus Clock Source Selection SMBCS1 The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or when the Free Timeout detection is enabled. When operating as a ...
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C8051F54x meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 20.2 shows the min- imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically necessary when SYSCLK is above ...
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SFR Definition 20.1. SMB0CF: SMBus Clock/Configuration Bit 7 6 Name ENSMB INH BUSY Type R/W R/W Reset 0 0 SFR Address = 0xC1; SFR Page = 0x00 Bit Name 7 ENSMB SMBus Enable. This bit enables the SMBus interface when ...
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C8051F54x 20.4.2. SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 20.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used ...
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SFR Definition 20.2. SMB0CN: SMBus Control Bit 7 6 Name MASTER TXMODE Type R R Reset 0 0 SFR Address = 0xC0; Bit-Addressable; SFR Page =0x00 Bit Name Description 7 MASTER SMBus Master/Slave Indicator. This read-only bit indicates when the ...
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C8051F54x Table 20.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When: MASTER A START is generated. TXMODE START is generated. SMB0DAT is written before the start of an SMBus frame. STA A START ...
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Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. ...
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C8051F54x 20.5.1. Write Sequence (Master) During a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be a transmitter during the address byte, and a transmitter during all data bytes. The SMBus ...
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Read Sequence (Master) During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface ...
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C8051F54x 20.5.3. Write Sequence (Slave) During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. When slave ...