C8051F986-GUR Silicon Labs, C8051F986-GUR Datasheet

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C8051F986-GUR

Manufacturer Part Number
C8051F986-GUR
Description
8-bit Microcontrollers - MCU 8kB 512B RAM 12b ADC
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F986-GUR

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Rev. 1.1 5/11
Ultra Low Power Consumption
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Supply Voltage 1.8 to 3.6 V
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12-Bit or 10-Bit Analog to Digital Converter
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Capacitive Sense Interface (F99x)
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Analog Comparator
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6-Bit Programmable Current Reference
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150 µA/MHz in active mode (24.5 MHz clock)
2 µs wakeup time
10 nA sleep mode with memory retention
50 nA sleep mode with brownout detector
300 nA sleep mode with LFO
600 nA sleep mode with external crystal
Built-in LDO regulator allows a high analog supply
voltage and low digital core voltage
2 built-in supply monitors (brownout detector) for
sleep mode and active modes
±1 LSB INL (10-bit mode); ±1.5 LSB INL 
(12-bit mode) no missing codes
Programmable throughput up to 300 ksps 
(10-bit mode) or 75 ksps (12-bit mode)
Up to 10 external inputs
On-chip voltage reference; 0.5x gain allows measur-
ing voltages up to twice the reference voltage
16-bit auto-averaging accumulator with burst mode
provides increased ADC resolution
Data dependent windowed interrupt generator
Built-in temperature sensor
Supports buttons, sliders, wheels, and capacitive
proximity sensing
Fast 40 µs per channel conversion time
16-bit resolution, up to 14 input channels
Auto scan and wake-on-touch
Auto-accumulate up to 64x samples
Programmable hysteresis and response time
Configurable as wake-up or reset source
Up to ±500 µA, can be used as a bias or for
generating a custom reference voltage
PWM enhanced resolution mode
Copyright © 2011 by Silicon Laboratories
Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU
SENSOR
ANALOG PERIPHERALS
INTERRUPTS
TEM P
Capacitive
M
A
U
X
INTERNAL OSCILLATOR
ISP FLASH
Sense
FLEXIBLE
24.5 M Hz PRECISION
8/4/2 kB
External Oscillator
75/300 ksps
HIGH-SPEED CONTROLLER CORE
VREG
12/10-bit
VREF
ADC
COM PAR ATO R
VOLTAG E
+
CIRCUITRY
8051 CPU
(25 M IPS)
IREF
DEBUG
HARDW ARE sm aRTClock
High-Speed 8051 µC Core
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Memory
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Digital Peripherals
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Clock Sources
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On-Chip Debug
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Packages
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Temperature Range: –40 to +85 °C
INTERNAL OSCILLATOR
Timer 0
Timer 1
Timer 2
Timer 3
20 MHz LOW POW ER
SM Bus
UART
PCA
CRC
C8051F99x-C8051F98x
SPI
DIGITAL I/O
Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler
512 bytes RAM
8 kB (F990/1/6/7, F980/1/6/7), 4 kB (F982/3/8/9), or
2 kB (F985) Flash; in-system programmable
Up to 17 port I/O; high sink current and
programmable drive strength
Hardware SMBus™/I
ports available concurrently
Four general purpose 16-bit counter/timers
Programmable 16-bit counter/timer array with three
capture/compare modules and watchdog timer
Internal oscillators: 24.5 MHz, 2% accuracy
supports UART operation; 20 MHz low power
oscillator requires very little bias current.
External oscillator: Crystal, RC, C, or CMOS Clock
SmaRTClock oscillator: 32 kHz Crystal or internal
Can switch between clock sources on-the-fly; useful
in implementing various power saving modes
On-chip debug circuitry facilitates full-speed, non-
intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping
Inspect/modify memory and registers
Complete development kit
20-pin QFN (3 x 3 mm)
24-pin QFN (4 x 4 mm)
24-pin QSOP (easy to hand-solder)
512B SRAM
POR
Port 2
Port 0
Port 1
W DT
2
C™, SPI™, and UART serial
C8051F99x-C8051F98x

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