C8051F707-GMR Silicon Labs, C8051F707-GMR Datasheet
C8051F707-GMR
Specifications of C8051F707-GMR
Related parts for C8051F707-GMR
C8051F707-GMR Summary of contents
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Capacitance to Digital Converter - Supports buttons, sliders, wheels, capacitive prox- imity, and touch screen sensing - input channels - Fast 40 µs per channel conversion time - 12, 13, 14, or 16-bit output - Auto-scan and ...
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C8051F70x/71x 2 Rev. 1.0 ...
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Table of Contents 1. System Overview ..................................................................................................... 17 2. Ordering Information ............................................................................................... 26 3. Pin Definitions.......................................................................................................... 28 4. TQFP-64 Package Specifications ........................................................................... 37 5. TQFP-48 Package Specifications ........................................................................... 39 6. QFN-48 Package Specifications ............................................................................. 41 7. QFN-32 Package Specifications ............................................................................. ...
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C8051F70x/71x 16.1.1. Instruction and CPU Timing .................................................................... 99 16.2. CIP-51 Register Descriptions ........................................................................ 104 17. Memory Organization .......................................................................................... 108 17.1. Program Memory........................................................................................... 109 17.1.1. MOVX Instruction and Program Memory .............................................. 109 17.2. EEPROM Memory ......................................................................................... 109 17.3. Data Memory ................................................................................................. ...
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Flash Erase Procedure ......................................................................... 148 22.1.3. Flash Write Procedure .......................................................................... 149 22.2. Non-volatile Data Storage ............................................................................. 149 22.3. Security Options ............................................................................................ 149 22.4. Flash Write and Erase Guidelines ................................................................. 150 22.4.1. VDD Maintenance and the VDD Monitor .............................................. 151 ...
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C8051F70x/71x 28.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 182 28.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 184 28.2.3. Assigning Port I/O Pins to External Event Trigger Functions................ 184 28.3. Priority Crossbar Decoder ............................................................................. 185 28.4. Port I/O ...
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Serial Clock Phase and Polarity .................................................................... 245 31.6. SPI Special Function Registers ..................................................................... 247 32. UART0 ................................................................................................................... 254 32.1. Enhanced Baud Rate Generation.................................................................. 255 32.2. Operational Modes ........................................................................................ 256 32.2.1. 8-Bit UART ............................................................................................ 256 32.2.2. 9-Bit UART ............................................................................................ 257 ...
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C8051F70x/71x List of Figures Figure 1.1. C8051F700/1 Block Diagram ................................................................ 18 Figure 1.2. C8051F702/3 Block Diagram ................................................................ 19 Figure 1.3. C8051F704/5 Block Diagram ................................................................ 20 Figure 1.4. C8051F706/07 Block Diagram .............................................................. 21 Figure 1.5. C8051F708/09/10/11 Block Diagram .................................................... 22 Figure ...
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Figure 18.3. EMIF Operating Modes ..................................................................... 117 Figure 18.4. Non-multiplexed 16-bit MOVX Timing ............................................... 120 Figure 18.5. Non-multiplexed 8-bit MOVX without Bank Select Timing ................ 121 Figure 18.6. Non-Multiplexed 8-Bit MOVX with Bank Select Timing ..................... 122 Figure 18.7. Multiplexed ...
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C8051F70x/71x Figure 32.6. UART Multi-Processor Mode Interconnect Diagram ......................... 258 Figure 33.1. T0 Mode 0 Block Diagram ................................................................. 265 Figure 33.2. T0 Mode 2 Block Diagram ................................................................. 266 Figure 33.3. T0 Mode 3 Block Diagram ................................................................. 267 Figure 33.4. Timer ...
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List of Tables Table 2.1. Product Selection Guide ......................................................................... 27 Table 3.1. Pin Definitions for the C8051F70x/71x ................................................... 28 Table 4.1. TQFP-64 Package Dimensions .............................................................. 37 Table 4.2. TQFP-64 PCB Land Pattern Dimensions ............................................... 38 Table 5.1. TQFP-48 Package Dimensions ...
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C8051F70x/71x Table 30.4. Hardware Address Recognition Examples (EHACK = 1) ................... 229 Table 30.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0) ...... 236 Table 30.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1) ...... 238 Table 31.1. ...
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List of Registers SFR Definition 10.1. ADC0CF: ADC0 Configuration .................................................... 59 SFR Definition 10.2. ADC0H: ADC0 Data Word MSB .................................................. 60 SFR Definition 10.3. ADC0L: ADC0 Data Word LSB .................................................... 60 SFR Definition 10.4. ADC0CN: ADC0 Control .............................................................. 61 SFR ...
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C8051F70x/71x SFR Definition 21.5. EIP1: Extended Interrupt Priority 1 ............................................ 144 SFR Definition 21.6. EIP2: Extended Interrupt Priority 2 ............................................ 145 SFR Definition 21.7. IT01CF: INT0/INT1 Configuration .............................................. 147 SFR Definition 22.1. PSCTL: Program Store R/W Control ......................................... 153 SFR ...
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SFR Definition 28.29. P4DRV: Port 4 Drive Strength ................................................. 206 SFR Definition 28.30. P5: Port 5 ................................................................................. 206 SFR Definition 28.31. P5MDIN: Port 5 Input Mode ..................................................... 207 SFR Definition 28.32. P5MDOUT: Port 5 Output Mode .............................................. 207 SFR Definition ...
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C8051F70x/71x SFR Definition 34.3. PCA0PWM: PCA PWM Configuration ....................................... 297 SFR Definition 34.4. PCA0CPMn: PCA Capture/Compare Mode .............................. 298 SFR Definition 34.5. PCA0L: PCA Counter/Timer Low Byte ...................................... 299 SFR Definition 34.6. PCA0H: PCA Counter/Timer High Byte ..................................... 299 SFR ...
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System Overview C8051F70x/71x devices are fully integrated, system-on-a-chip, capacitive sensing mixed-signal MCUs. Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers. High-speed pipelined 8051-compatible microcontroller core ( MIPS) ...
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C8051F70x/71x CIP-51 8051 Controller Core Power On Reset 15 kB Flash Memory Reset 256 Byte RAM Debug / C2CK/RST 256 Byte XRAM Programming C2D Hardware 32 Bytes EEPROM Peripheral Power SYSCLK VDD Regulator Core Power Precision GND Internal Oscillator External ...
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CIP-51 8051 Controller Core Power On Reset 16 kB Flash Memory Reset 256 Byte RAM Debug / C2CK/RST Programming 256 Byte XRAM C2D Hardware Peripheral Power SYSCLK VDD Regulator Core Power Precision GND Internal Oscillator External XTAL1 Clock XTAL2 Circuit ...
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C8051F70x/71x CIP-51 8051 Controller Core Power On Reset 15 kB Flash Memory Reset 256 Byte RAM Debug / C2CK/RST 256 Byte XRAM Programming C2D Hardware 32 Bytes EEPROM Peripheral Power SYSCLK VDD Regulator Core Power Precision GND Internal Oscillator External ...
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CIP-51 8051 Controller Core Power On Reset 16 kB Flash Memory Reset 256 Byte RAM Debug / C2CK/RST Programming 256 Byte XRAM C2D Hardware Peripheral Power SYSCLK VDD Regulator Core Power Precision GND Internal Oscillator External XTAL1 Clock XTAL2 Circuit ...
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C8051F70x/71x CIP-51 8051 Controller Core Power On Reset 8 kB Flash Memory Reset 256 Byte RAM Debug / C2CK/RST 256 Byte XRAM Programming C2D Hardware 32 Bytes EEPROM (‘F708/09 Only) Peripheral Power SYSCLK VDD Regulator Core Power Precision GND Internal ...
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CIP-51 8051 Controller Core Power On Reset 8 kB Flash Memory Reset 256 Byte RAM Debug / C2CK/RST Programming 256 Byte XRAM C2D Hardware 32 Bytes EEPROM (‘F712/13 Only) Peripheral Power SYSCLK VDD Regulator Core Power Precision GND Internal Oscillator ...
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C8051F70x/71x CIP-51 8051 Controller Core Power On Reset 16 kB Flash Memory Reset 256 Byte RAM Debug / C2CK/RST Programming 256 Byte XRAM C2D Hardware Peripheral Power SYSCLK VDD Regulator Core Power Precision GND Internal Oscillator External XTAL1 Clock XTAL2 ...
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CIP-51 8051 Controller Core Power On Reset 16 kB Flash Memory Reset 256 Byte RAM Debug / C2CK/RST Programming 256 Byte XRAM C2D Hardware Peripheral Power SYSCLK VDD Regulator Core Power Precision GND Internal Oscillator External XTAL1 Clock XTAL2 Circuit ...
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C8051F70x/71x 2. Ordering Information All C8051F70x/71x devices have the following features: 25 MIPS (Peak) Calibrated Internal Oscillator 2 SMBus/I C UART Programmable counter array (3 channels) 4 Timers (16-bit) 1 Comparator Pb-Free ...
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... C8051F701- C8051F702- C8051F703- C8051F704- C8051F704- C8051F705- C8051F705- C8051F706- C8051F706- C8051F707- C8051F707- C8051F708- C8051F709- C8051F710- C8051F711- C8051F712- C8051F712- C8051F713- C8051F713- C8051F714- C8051F714-GM ...
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C8051F70x/71x 3. Pin Definitions Table 3.1. Pin Definitions for the C8051F70x/71x Name TQFP64 TQFP48 QFN32 QFN24 QFN48 V 8, 24 41, 57 GND 9, 25, 9, 21, Center 40, 56 30, 43 RST / 58 ...
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Table 3.1. Pin Definitions for the C8051F70x/71x (Continued) Name TQFP64 TQFP48 QFN32 QFN24 QFN48 P0 — P1 — P1 — P1 — P1 — P1.4 43 — — P1.5 42 ...
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C8051F70x/71x Table 3.1. Pin Definitions for the C8051F70x/71x (Continued) Name TQFP64 TQFP48 QFN32 QFN24 QFN48 P3.0 29 — 15 P3.1 28 — 14 P3.2 27 — 13 P3.3 26 — P3.6 ...
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Table 3.1. Pin Definitions for the C8051F70x/71x (Continued) Name TQFP64 TQFP48 QFN32 QFN24 QFN48 P5.7 2 ...
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C8051F70x/71x P6.0 1 P5.7 2 P5.6 3 P5.5 4 P5.4 5 P5.3 6 P5.2 7 VDD 8 C8051F700/01/02/03/08/09/10/11 GND 9 P5.1 10 P5.0 11 P4.7 12 P4.6 13 P4.5 14 P4.4 15 P4.3 16 Figure 3.1. C8051F7xx-GQ TQFP64 Pinout Diagram ...
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P6.3 1 P5.7 2 P5.6 3 P5.5 4 P5.4 5 C8051F704/05/06/07/ P5.3 6 P5.2 7 VDD 8 GND 9 P5.1 10 P5.0 11 P4.3 12 Figure 3.2. C8051F7xx-GQ QFP48 Pinout Diagram (Top View) C8051F70x/71x 12/13/14/15 Rev. 1.0 P0.6 36 P0.7 ...
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C8051F70x/71x 1 P6.3 P5.7 2 P5.6 3 P5.5 4 P5.4 5 C8051F704/05/06/07/ P5.3 6 P5.2 7 VDD 8 GND 9 P5.1 10 P5.0 11 P4.3 12 Figure 3.3. C8051F7xx-GM QFN48 Pinout Diagram (Top View) 34 12/13/14/15 GND Rev. 1.0 36 ...
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P5.7 1 P5.6 2 P5.5 3 P5.4 4 C8051F716 P5.3 5 P5.2 6 P5.1 7 P5.0 8 Figure 3.4. C8051F716-GM QFN32 Pinout Diagram (Top View) C8051F70x/71x GND Rev. 1.0 24 P0.5 23 P2.0 22 P2.1 21 P2.2 20 P2.3 19 ...
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C8051F70x/71x P6.4 1 P4.7 2 P4.6 3 P4.5 4 P4.4 5 P4.3 6 Figure 3.5. C8051F717-GM QFN24 Pinout Diagram (Top View) 36 C8051F717 GND Rev. 1.0 18 P0.5 17 P2.0 16 P2.1 15 P2.2 14 P2.3 13 P2.4 ...
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TQFP-64 Package Specifications Figure 4.1. TQFP-64 Package Drawing Table 4.1. TQFP-64 Package Dimensions Dimension Min Nom A — — A1 0.05 — A2 0.95 1.00 b 0.17 0.22 c 0.09 — D 12.00 BSC. D1 10.00 BSC. e 0.50 ...
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C8051F70x/71x Figure 4.2. TQFP-64 PCB Land Pattern Table 4.2. TQFP-64 PCB Land Pattern Dimensions Dimension Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based ...
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TQFP-48 Package Specifications Figure 5.1. TQFP-48 Package Drawing Table 5.1. TQFP-48 Package Dimensions Dimension Min Nom A — — A1 0.05 — A2 0.95 1.00 b 0.17 0.22 c 0.09 — D 9.00 BSC. D1 7.00 BSC. e ...
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C8051F70x/71x Figure 5.2. TQFP-48 PCB Land Pattern Table 5.2. TQFP-48 PCB Land Pattern Dimensions Dimension Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based ...
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QFN-48 Package Specifications Figure 6.1. QFN-48 Package Drawing Table 6.1. QFN-48 Package Dimensions Dimension Min Nom A 0.80 0.90 A1 0.00 — b 0.18 0.23 D 7.00 BSC. D2 3.90 4.00 e 0.50 BSC. E 7.00 BSC. Notes: ...
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C8051F70x/71x Figure 6.2. QFN-48 PCB Land Pattern Table 6.2. QFN-48 PCB Land Pattern Dimensions Dimension Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing ...
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QFN-32 Package Specifications Figure 7.1. QFN-32 Package Drawing Table 7.1. QFN-32 Package Dimensions Dimension Min Typ A 0.80 0.90 A1 0.00 0.02 b 0.18 0.25 D 5.00 BSC. D2 3.50 3.60 e 0.50 BSC. E 5.00 BSC. Notes: 1. ...
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C8051F70x/71x Figure 7.2. QFN-32 Recommended PCB Land Pattern Table 7.2. QFN-32 PCB Land Pattern Dimensions Dimension Min C1 4.60 C2 4.60 E 0.50 X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning ...
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QFN-24 Package Specifications Figure 8.1. QFN-24 Package Drawing Table 8.1. QFN-24 Package Dimensions Dimension Min Typ A 0.70 0.75 A1 0.00 0.02 b 0.18 0.25 D 4.00 BSC. D2 2.55 2.70 e 0.50 BSC. E 4.00 BSC. E2 2.55 ...
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C8051F70x/71x Figure 8.2. QFN-24 Recommended PCB Land Pattern Table 8.2. QFN-24 PCB Land Pattern Dimensions Dimension Min C1 3.90 C2 3.90 E 0.50 BSC X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. ...
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Electrical Characteristics 9.1. Absolute Maximum Specifications Table 9.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on RST or any Port I/O Pin (except P0.3) with respect to GND Voltage on P0.3 with respect to GND ...
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C8051F70x/71x 9.2. Electrical Characteristics Table 9.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter 1 Supply Voltage Digital Supply Current with 2,3 CPU Active (Normal Mode ) Digital Supply Current with 2,3 CPU ...
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Table 9.3. Port I/O DC Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters Conditions Output High Voltage High Drive Strength I = –3 mA, Port I/O push-pull –10 ...
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C8051F70x/71x Table 9.5. Internal Voltage Regulator Electrical Characteristics V –40 to +85 °C unless otherwise specified Parameter Input Voltage Range Bias Current Table 9.6. Flash Electrical Characteristics Parameter Flash Size* Endurance (Erase/Write) Erase Cycle Time Write ...
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Table 9.8. Capacitive Sense Electrical Characteristics V = 1 –40 to +85 °C unless otherwise specified Parameter 1 Single Conversion Time Number of Channels Capacitance per Code External Capacitive Load External Series Impedance ...
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C8051F70x/71x Table 9.9. EEPROM Electrical Characteristics V = 1 –40 to +85 °C unless otherwise specified. Use factory-calibrated settings Parameter Write to EEPROM from RAM Read of EEPROM to RAM Endurance (Writes) Clock ...
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Table 9.11. Power Management Electrical Characteristics V = 1 –40 to +85 °C unless otherwise specified. Use factory-calibrated settings Parameter Idle Mode Wake-Up time Suspend Mode Wake-Up Time Table 9.12. Temperature Sensor Electrical ...
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C8051F70x/71x Table 9.14. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. DD Parameter Response Time: * Mode 0, Vcm = 1.5 V Response Time: * Mode 1, Vcm = 1.5 V Response Time: * ...
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ADC (ADC0) ADC0 on the C8051F700/2/4/6/8 and C8051F710/2/4 500 ksps, 10-bit successive-approximation- register (SAR) ADC with integrated track-and-hold, a gain stage programmable 0.5x, and a pro- grammable window detector. The ADC is fully ...
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C8051F70x/71x 10.1. Output Code Formatting The ADC measures the input voltage with reference to GND. The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion. ...
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Tracking Modes The AD0TM bit in register ADC0CN enables "delayed conversions", and will delay the actual conversion start by three SAR clock cycles, during which time the ADC will continue to track the input. If AD0TM is left at ...
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C8051F70x/71x 10.3.3. Settling Time Requirements A minimum tracking time is required before each conversion to ensure that an accurate conversion is per- formed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the the ADC0 sampling ...
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SFR Definition 10.1. ADC0CF: ADC0 Configuration Bit 7 6 AD0SC[4:0] Name Type 1 1 Reset SFR Address = 0xBC; SFR Page = F Bit Name 7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system ...
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C8051F70x/71x SFR Definition 10.2. ADC0H: ADC0 Data Word MSB Bit 7 6 Name Type 0 0 Reset SFR Address = 0xBE; SFR Page = 0 Bit Name 7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7:2 ...
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SFR Definition 10.4. ADC0CN: ADC0 Control Bit 7 6 AD0EN AD0TM AD0INT Name R/W R/W Type 0 0 Reset SFR Address = 0xE8; SFR Page = All Pages; Bit-Addressable Bit Name 7 AD0EN ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 ...
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C8051F70x/71x 10.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code ...
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SFR Definition 10.7. ADC0LTH: ADC0 Less-Than Data High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xC6; SFR Page = 0 Bit Name 7:0 ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits. SFR Definition 10.8. ADC0LTL: ADC0 ...
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C8051F70x/71x 10.4.1. Window Detector Example Figure 10.4 shows two example ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit ...
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ADC0 Analog Multiplexer ADC0 on the C8051F700/2/4/6/8 and C8051F710/2/4/6 uses an analog input multiplexer to select the pos- itive input to the ADC. Any of the following may be selected as the positive input: Port 0 or Port 1 ...
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C8051F70x/71x SFR Definition 10.9. ADC0MX: AMUX0 Channel Select Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xBB; SFR Page = 0 Bit Name 7:5 Unused Read = 000b; Write = Don’t Care. 4:0 AMX0P[4:0] AMUX0 ...
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Temperature Sensor An on-chip temperature sensor is included on the C8051F700/2/4/6/8 and C8051F710/2/4/6 which can be directly accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the temperature sensor, the ADC mux channel should ...
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C8051F70x/71x Parameters that affect ADC measurement, in particular the voltage reference value, will also affect temper- ature measurement. 5.00 4.00 3.00 2.00 1.00 0.00 -40.00 -20.00 -1.00 -2.00 -3.00 -4.00 -5.00 Figure 11.2. Temperature Sensor Error with 1-Point Calibration at ...
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Voltage and Ground Reference Options The voltage reference MUX is configurable to use an externally connected voltage reference, the on-chip voltage reference, or one of two power supply voltages (see Figure 12.1). The ground reference MUX allows the ground ...
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C8051F70x/71x 12.1. External Voltage References To use an external voltage reference, REFSL[1:0] should be set to 00. Bypass capacitors should be added as recommended by the manufacturer of the external voltage reference. 12.2. Internal Voltage Reference Options A 1.6 V ...
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SFR Definition 12.1. REF0CN: Voltage Reference Control Bit 7 6 REFGND Name R R Type 0 0 Reset SFR Address = 0xD2; SFR Page = F Bit Name 7:6 Unused Read = 00b; Write = Don’t Care. 5 REFGND Analog ...
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C8051F70x/71x 13. Voltage Regulator (REG0) C8051F70x/71x devices include an internal voltage regulator (REG0) to regulate the internal core supply to 1.8 V from a V supply of 1.8 to 3.6 V. Two power-saving modes are built into the regulator to ...
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SFR Definition 13.1. REG0CN: Voltage Regulator Control Bit 7 6 STOPCF BYPASS Name R/W R/W Type 0 0 Reset SFR Address = 0xB9; SFR Page = F Bit Name 7 STOPCF Stop Mode Configuration. This bit configures the regulator’s behavior ...
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C8051F70x/71x 14. Comparator0 C8051F70x/71x devices include an on-chip programmable voltage comparator, Comparator0, shown in Figure 14.1. The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a ...
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The Comparator response time may be configured in software via the CPT0MD register (see SFR Defini- tion 14.2). Selecting a longer response time reduces the Comparator supply current. CP0+ VIN+ + CP0 CP0- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage ...
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C8051F70x/71x SFR Definition 14.1. CPT0CN: Comparator0 Control Bit 7 6 CP0EN CP0OUT CP0RIF Name R/W R Type 0 0 Reset SFR Address = 0x9B; SFR Page = 0 Bit Name 7 CP0EN Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 ...
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SFR Definition 14.2. CPT0MD: Comparator0 Mode Selection Bit 7 6 CP0RIE Name R R Type 0 0 Reset SFR Address = 0x9D; SFR Page = 0 Bit Name 7:6 Unused Read = 00b, Write = Don’t Care. 5 CP0RIE Comparator0 ...
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C8051F70x/71x 14.1. Comparator Multiplexer C8051F70x/71x devices include an analog input multiplexer to connect Port I/O pins to the comparator inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 14.3). The CMX0P2– CMX0P0 bits select the Comparator0 positive ...
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SFR Definition 14.3. CPT0MX: Comparator0 MUX Selection Bit 7 6 CMX0N[2:0] Name R Type 0 0 Reset SFR Address = 0x9F; SFR Page = 0 Bit Name 7 Unused Read = 0b; Write = don’t care. 6:4 CMX0N[2:0] Comparator0 Negative ...
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C8051F70x/71x 15. Capacitive Sense (CS0) The Capacitive Sense subsystem uses a capacitance-to-digital circuit to determine the capacitance on a port pin. The module can take measurements from different port pins using the module’s analog multi- plexer. The module is enabled ...
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Configuring Port Pins as Capacitive Sense Inputs In order for a port pin to be measured by CS0, that port pin must be configured as an analog input (see “28. Port Input/Output” ). Configuring the input multiplexer to a ...
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C8051F70x/71x If CS0BUSY is used to initiate conversions, and then polled to determine if the conversion is finished, at least one clock cycle must be inserted between setting CS0BUSY to 1 and polling the CS0BUSY bit. Conversions can be configured ...
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Automatic Scanning CS0 can be configured to automatically scan a sequence of contiguous CS0 input channels by configuring and enabling auto-scan. Using auto-scan with the CS0 comparator interrupt enabled allows a system to detect a change in measured capacitance ...
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C8051F70x/71x 15.5. CS0 Comparator The CS0 comparator compares the latest capacitive sense conversion result with the value stored in CS0THH:CS0THL. If the result is less than or equal to the stored value, the CS0CMPF bit(CS0CN:0) is set ...
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CS0 Conversion Accumulator CS0 can be configured to accumulate multiple conversions on an input channel. The number of samples to be accumulated is configured using the CS0ACU2:0 bits (CS0CF2:0). The accumulator can accumulate 16, 32, or ...
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C8051F70x/71x 15.7. CS0 Pin Monitor The CS0 module provides accurate conversions in all operating modes of the CPU, peripherals and I/O ports. Pin monitoring circuits are provided to improve interference immunity from high-current output pin switching. The Capacitive Sense Pin ...
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Adjusting CS0 For Special Situations There are several configuration options in the CS0 module designed to modify the operation of the circuit and address special situations. In particular, any circuit with more than 500 of series impedance between ...
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C8051F70x/71x SFR Definition 15.1. CS0CN: Capacitive Sense Control Bit 7 6 Name CS0EN CS0PME CS0INT Type R/W R/W Reset 0 0 SFR Address = 0x9A; SFR Page = 0 Bit Name 7 CS0EN CS0 Enable. 0: CS0 disabled and in ...
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SFR Definition 15.2. CS0CF: Capacitive Sense Configuration Bit 7 6 Name CS0CM[2:0] Type R R/W Reset 0 0 SFR Address = 0x9E; SFR Page = 0 Bit Name 7 Unused Read = 0b; Write = Don’t care 6:4 CS0CM[2:0] CS0 ...
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C8051F70x/71x SFR Definition 15.3. CS0DH: Capacitive Sense Data High Byte Bit 7 6 Name Type R R Reset 0 0 SFR Address = 0xAA; SFR Page = 0 Bit Name 7:0 CS0DH CS0 Data High Byte. Stores the high byte ...
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SFR Definition 15.5. CS0SS: Capacitive Sense Auto-Scan Start Channel Bit 7 6 Name Type R R Reset 0 0 SFR Address = 0x92; SFR Page = F Bit Name 7:6 Unused Read = 00b; Write = Don’t care 5:0 CS0SS[5:0] ...
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C8051F70x/71x SFR Definition 15.7. CS0THH: Capacitive Sense Comparator Threshold High Byte Bit 7 6 Name Type R/W R/W Reset 0 0 SFR Address = 0x97; SFR Page = 0 Bit Name 7:0 CS0THH[7:0] CS0 Comparator Threshold High Byte. High byte ...
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SFR Definition 15.9. CS0PM: Capacitive Sense Pin Monitor Bit 7 6 Name UAPM SPIPM SMBPM Type R/W R/W Reset 0 0 SFR Address = 0x9F; SFR Page = F Bit Name 7 UAPM UART Pin Monitor Enable. Enables monitoring of ...
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C8051F70x/71x SFR Definition 15.10. CS0MD1: Capacitive Sense Mode 1 Bit 7 6 Name Type R Reset 0 0 SFR Address = 0xAD; SFR Page = 0 Bit Name 7:6 Unused Read = 00b; Write = Don’t care 5:4 CS0DR[1:0] CS0 ...
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SFR Definition 15.11. CS0MD2: Capacitive Sense Mode 2 Bit 7 6 Name CS0CR[1:0] Type R/W Reset 0 1 SFR Address = 0xBE; SFR Page = F Bit Name 7:6 CS0CR[1:0] CS0 Conversion Rate. These bits control the conversion rate of ...
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C8051F70x/71x 15.9. Capacitive Sense Multiplexer The input multiplexer can be controlled through two methods. The CS0MX register can be written to through firmware, or the register can be configured automatically using the modules auto-scan functionality (see “15.4. Automatic Scanning” ). ...
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SFR Definition 15.12. CS0MX: Capacitive Sense Mux Channel Select Bit 7 6 CS0UC Name R/W R/W Type 0 0 Reset SFR Address = 0x9C; SFR Page = 0 Bit Name 7 CS0UC CS0 Unconnected. Disconnects CS0 from all port pins, ...
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C8051F70x/71x 16. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a ...
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With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execu- tion time. ...
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C8051F70x/71x Table 16.1. CIP-51 Instruction Set Summary Mnemonic Description Arithmetic Operations ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to ...
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Table 16.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement Rotate A left RLC A Rotate A left through Carry RR A Rotate ...
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C8051F70x/71x Table 16.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description ANL C, bit AND direct bit to Carry ANL C, /bit AND complement of direct bit to Carry ORL C, bit OR direct bit to carry ORL C, /bit OR ...
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Notes on Registers, Operands and Addressing Modes: Rn—Register R0–R7 of the currently selected register bank. @Ri—Data RAM location addressed indirectly through R0 or R1. rel—8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by ...
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C8051F70x/71x 16.2. CIP-51 Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should always be written to the value indicated in the SFR description. Future product versions may use these bits ...
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SFR Definition 16.3. SP: Stack Pointer Bit 7 6 Name Type 0 0 Reset SFR Address = 0x81; SFR Page = All Pages Bit Name 7:0 SP[7:0] Stack Pointer. The Stack Pointer holds the location of the top of the ...
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C8051F70x/71x SFR Definition 16. Register Bit 7 6 Name Type 0 0 Reset SFR Address = 0xF0; SFR Page = All Pages; Bit-Addressable Bit Name 7:0 B[7:0] B Register. This register serves as a second accumulator for certain ...
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SFR Definition 16.6. PSW: Program Status Word Bit Name R/W R/W Type 0 0 Reset SFR Address = 0xD0; SFR Page = All Pages; Bit-Addressable Bit Name 7 CY Carry Flag. This bit is set when ...
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C8051F70x/71x 17. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space ...
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Program Memory The members of the C8051F70x/71x device family contain 16 kB (C8051F702/3/6/7 and C8051F16/7 (C8051F700/1/4/5 (C8051F708/9 and C8051F710/1/2/3/4/5) of re-programmable Flash memory that can be used as non-volatile program or data storage. The ...
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C8051F70x/71x byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. The upper 128 bytes of data memory are accessible only by indirect ...
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External Data Memory Interface and On-Chip XRAM For C8051F70x/71x devices, 256 B of RAM are included on-chip and mapped into the external data mem- ory space (XRAM). Additionally, an External Memory Interface (EMIF) is available on the C8051F700/1/2/3/8/9 and ...
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C8051F70x/71x 18.2. Configuring the External Memory Interface Configuring the External Memory Interface consists of five steps: 1. Configure the Output Modes of the associated port pins as either push-pull or open-drain (push-pull is most common). 2. Configure Port latches to ...
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SFR Definition 18.1. EMI0CN: External Memory Interface Control Bit 7 6 Name Type Reset 0 0 SFR Address = 0xAA; SFR Page = F Bit Name 7:0 PGSEL[7:0] XRAM Page Select Bits. The XRAM Page Select Bits provide the high ...
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C8051F70x/71x SFR Definition 18.2. EMI0CF: External Memory Configuration Bit 7 6 Name Type R Reset 0 0 SFR Address = 0xC7; SFR Page = F Bit Name 7:5 Unused Read = 000b; Write = Don’t Care. 4 EMD2 EMIF Multiplex ...
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Multiplexed and Non-multiplexed Selection The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode, depending on the state of the EMD2 (EMI0CF.4) bit. 18.4.1. Multiplexed Configuration In Multiplexed mode, the Data Bus and ...
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C8051F70x/71x 18.4.2. Non-multiplexed Configuration In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a Non- multiplexed Configuration is shown in Figure 18.2. See Section “18.6.1. Non-Multiplexed Mode” on page 120 for more ...
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Memory Mode Selection The external data memory space can be configured in one of four modes, shown in Figure 18.3, based on the EMIF Mode bits in the EMI0CF register (SFR Definition 18.2). These modes are summarized below. More ...
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C8051F70x/71x 18.5.3. Split Mode with Bank Select When EMI0CF[3:2] are set to 10, the XRAM memory map is split into two areas, on-chip space and off- chip space. Effective addresses below the internal XRAM size boundary will access on-chip ...
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SFR Definition 18.3. EMI0TC: External Memory Timing Control Bit 7 6 EAS[1:0] Name R/W Type 1 1 Reset SFR Address = 0xEE; SFR Page = F Bit Name 7:6 EAS[1:0] EMIF Address Setup Time Bits. 00: Address setup time = ...
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C8051F70x/71x 18.6.1. Non-Multiplexed Mode 18.6.1.1. 16-bit MOVX: EMI0CF[4:2] = 101, 110, or 111 ADDR[15:8] ADDR[7:0] DATA[7: ADDR[15:8] ADDR[7:0] DATA[7: Figure 18.4. Non-multiplexed 16-bit MOVX Timing 120 Nonmuxed 16-bit WRITE EMIF ADDRESS (8 MSBs) from DPH EMIF ...
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MOVX without Bank Select: EMI0CF[4:2] = 101 or 111 ADDR[15:8] ADDR[7:0] DATA[7: ADDR[15:8] ADDR[7:0] DATA[7: Figure 18.5. Non-multiplexed 8-bit MOVX without Bank Select Timing Nonmuxed 8-bit WRITE without Bank Select EMIF ADDRESS (8 LSBs) ...
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C8051F70x/71x 18.6.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 110 ADDR[15:8] ADDR[7:0] DATA[7: ADDR[15:8] ADDR[7:0] DATA[7: Figure 18.6. Non-Multiplexed 8-Bit MOVX with Bank Select Timing 122 Nonmuxed 8-bit WRITE with Bank Select EMIF ADDRESS (8 MSBs) ...
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Multiplexed Mode 18.6.2.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] T ALEH ALE WR RD ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] T ALEH ALE RD WR Figure 18.7. Multiplexed 16-bit ...
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C8051F70x/71x 18.6.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE WR RD ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE ...
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MOVX with Bank Select: EMI0CF[4:2] = 010 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE WR RD ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE RD WR Figure ...
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C8051F70x/71x Table 18.1. AC Parameters for External Memory Interface Parameter Description T Address/Control Setup Time ACS T Address/Control Pulse Width ACW T Address/Control Hold Time ACH T Address Latch Enable High Time ALEH T Address Latch Enable Low Time ALEL ...
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Table 18.2. EMIF Pinout (C8051F700/1/2/3/8/9 and C8051F710/1) Multiplexed Mode Signal Name Port Pin RD P6.1 WR P6.0 ALE P6.2 D0/A0 P5.0 D1/A1 P5.1 D2/A2 P5.2 D3/A3 P5.3 D4/A4 P5.4 D5/A5 P5.5 D6/A6 P5.6 D7/A7 P5.7 A8 P4.0 A9 P4.1 A10 ...
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... Derivative Identification Byte. Shows the C8051F70x/71x derivative being used. 0xD0: C8051F700; 0xD1: C8051F701; 0xD2: C8051F702; 0xD3: C8051F703 0xD4: C8051F704; 0xD5: C8051F705; 0xD6: C8051F706; 0xD7: C8051F707 0xD8: C8051F708; 0xD9: C8051F709; 0xDA: C8051F710; 0xDB: C8051F711 0xDC: C8051F712; 0xDD: C8051F713; 0xDE: C8051F714; 0xDF: C8051F715 0xE0: C8051F716 ...
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SFR Definition 19.3. REVID: Hardware Revision Identification Byte Bit 7 6 Name R R Type Varies Varies Varies Reset SFR Address = 0xAD; SFR Page = F Bit Name 7:0 REVID[7:0] Hardware Revision Identification Byte. Shows the C8051F70x/71x hardware revision ...
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C8051F70x/71x 20. Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the C8051F70x/71x's resources and peripher- als. The CIP-51 controller core duplicates the ...
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Table 20.1. Special Function Register (SFR) Memory Map Addr SFR 0(8) 1(9) Page 0 PCA0L F8 SPI0CN F P0DRV P0MDIN 0 PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 E8 ADC0CN F 0 P1MAT E0 ACC F XBR0 0 D8 ...
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C8051F70x/71x SFR Definition 20.1. SFRPAGE: SFR Page Bit 7 6 Name Type 0 0 Reset SFR Address = 0xA7; SFR Page = All Pages Bit Name 7:0 SFRPAGE[7:0] SFR Page Bits. Represents the SFR Page the C8051 core uses when ...
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Table 20.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Page CS0CN 0x9A CS0DH 0xAA CS0DL 0xA9 CS0CF 0x9E CS0MD1 0xAD CS0MD2 0xBE CS0MX 0x9C CS0PM 0x9F CS0SE 0x93 CS0SS ...
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C8051F70x/71x Table 20.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Page P0MDIN 0xF1 P0MDOUT 0xA4 P0SKIP 0xD4 P1 0x90 All Pages Port 1 Latch P1DRV 0xFA P1MASK 0xE2 P1MAT ...
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Table 20.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Page PCA0CPM0 0xDA PCA0CPM1 0xDB PCA0CPM2 0xDC PCA0H 0xFA PCA0L 0xF9 PCA0MD 0xED PCA0PWM 0xA1 PCON 0x87 All Pages Power ...
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C8051F70x/71x Table 20.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Page TMR3CN 0x91 TMR3H 0x95 TMR3L 0x94 TMR3RLH 0x93 TMR3RLL 0x92 VDM0CN 0xFF All Pages VDD Monitor Control WDTCN ...
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Interrupts The C8051F70x/71x includes an extended interrupt system supporting several interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins var- ies according to the specific version of the device. Each ...
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C8051F70x/71x 21.1. MCU Interrupt Sources and Vectors The C8051F70x/71x MCUs support 16 interrupt sources. Software can simulate an interrupt by setting an interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated ...
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Table 21.1. Interrupt Summary Interrupt Source Interrupt Vector Reset 0x0000 External Interrupt 0 0x0003 (INT0) Timer 0 Overflow 0x000B External Interrupt 1 0x0013 (INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B Port Match ...
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C8051F70x/71x 21.2. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described in this section. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt ...
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SFR Definition 21.2. IP: Interrupt Priority Bit 7 6 PSPI0 Name R R/W Type 1 0 Reset SFR Address = 0xB8; SFR Page = All Pages; Bit-Addressable Bit Name 7 Unused Read = 1b, Write = Don't Care. 6 PSPI0 ...
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C8051F70x/71x SFR Definition 21.3. EIE1: Extended Interrupt Enable 1 Bit 7 6 ET3 Reserved Name R/W R/W Type 0 0 Reset SFR Address = 0xE6; SFR Page = All Pages Bit Name 7 ET3 Enable Timer 3 Interrupt. This bit ...
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SFR Definition 21.4. EIE2: Extended Interrupt Enable 2 Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xE7; SFR Page = All Pages Bit Name 7:2 Unused Read = 000000b; Write = don’t care. 1 ECSGRT ...
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C8051F70x/71x SFR Definition 21.5. EIP1: Extended Interrupt Priority 1 Bit 7 6 PT3 Reserved Name R/W R/W Type 0 0 Reset SFR Address = 0xCE; SFR Page = F Bit Name 7 PT3 Timer 3 Interrupt Priority Control. This bit ...
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SFR Definition 21.6. EIP2: Extended Interrupt Priority 2 Bit 7 6 Name Reserved Reserved Reserved R R Type 0 0 Reset SFR Address = 0xCF; SFR Page = F Bit Name 7:2 Reserved Must Write 000000b. 1 PSCGRT Capacitive Sense ...
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C8051F70x/71x 21.3. INT0 and INT1 External Interrupts The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select ...
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SFR Definition 21.7. IT01CF: INT0/INT1 Configuration Bit 7 6 IN1PL IN1SL[2:0] Name R/W Type 0 0 Reset SFR Address = 0xE4; SFR Page = F Bit Name 7 IN1PL INT1 Polarity. 0: INT1 input is active low. 1: INT1 input ...
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C8051F70x/71x 22. Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system through the C2 interface or by software using the MOVX write instruction. Once cleared to logic ...
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Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased. 7. Clear the PSWE and PSEE bits. 8. Restore previous interrupt state. Steps 4–6 must be repeated for each 512-byte page ...
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C8051F70x/71x unlocked pages, and user firmware executing on locked pages. Table 22.1 summarizes the Flash security features of the C8051F70x/71x devices. Table 22.1. Flash Security Summary Action Read, Write or Erase unlocked pages (except page with Lock Byte) Read, Write ...
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The following guidelines are recommended for any system that contains routines which write or erase Flash from code. 22.4.1. VDD Maintenance and the VDD Monitor 1. If the system power supply is subject to voltage or current "spikes," add sufficient ...
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C8051F70x/71x 22.4.3. System Clock 12.If operating from an external crystal, be advised that crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature. If the system is operating in an electrically noisy environment, ...
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SFR Definition 22.1. PSCTL: Program Store R/W Control Bit 7 6 Name R R Type 0 0 Reset SFR Address =0x8F; SFR Page = All Pages Bit Name 7:2 Unused Read = 000000b, Write = don’t care. 1 PSEE Program ...
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C8051F70x/71x SFR Definition 22.2. FLKEY: Flash Lock and Key Bit 7 6 Name Type 0 0 Reset SFR Address = 0xB7; SFR Page = All Pages Bit Name 7:0 FLKEY[7:0] Flash Lock and Key Register. Write: This register provides a ...
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EEPROM C8051F700/1/4/5/8/9 and C8051F712/3 devices have hardware which emulates 32 bytes of non-volatile, byte-programmable EEPROM data space. The module mirrors each non-volatile byte through 32 bytes of volatile data space. This data space can be accessed indirectly through EEADDR ...
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C8051F70x/71x 23.4. EEPROM Security RAM can only be downloaded to EEPROM after firmware writes a sequence of two bytes to EEKEY. In order to enable EEPROM writes: 1. Write the first EEPROM key code byte to EEKEY: 0x55 2. Write ...
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SFR Definition 23.2. EEDATA: EEPROM Byte Data Bit 7 6 Name Type 1 1 Reset SFR Address = 0xD1; SFR Page = All Pages Bit Name Description 7:0 EEDATA[7:0] E2PROM Data The EEDATA register is used to read bytes from ...
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C8051F70x/71x SFR Definition 23.3. EECNTL: EEPROM Control Bit 7 6 EEEN Name R/W Type 0 0 Reset SFR Address = 0xC5; SFR Page = F Bit Name 7 EEEN EEPROM Enable. 0: EEPROM control logic disabled. 1: EEPROM control logic ...
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SFR Definition 23.4. EEKEY: EEPROM Protect Key Bit 7 6 Name Type 0 0 Reset SFR Address = 0xC6; SFR Page = F Bit Name Description 7:0 EEKEY EEPROM Key. Protects the EEPROM from inadvertent writes and erases. 1:0 EEPSTATE ...
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C8051F70x/71x 24. Power Management Modes The C8051F70x/71x devices have three software programmable power management modes: Idle, Stop, and Suspend. Idle mode and Stop mode are part of the standard 8051 architecture, while Suspend mode is an enhanced power-saving mode implemented ...
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Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter Stop mode as soon as the instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripherals ...
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C8051F70x/71x SFR Definition 24.1. PCON: Power Control Bit 7 6 Name Type 0 0 Reset SFR Address = 0x87; SFR Page = All Pages Bit Name 7:2 GF[5:0] General Purpose Flags 5–0. These are general purpose flags for use under ...
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Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: CIP-51 halts program execution Special Function Registers (SFRs) are initialized to their defined ...
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C8051F70x/71x 25.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until delay occurs before the device is released from reset; the delay decreases as the ...
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Power-Fail Reset / V DD When a power-down transition or power irregularity causes V monitor will drive the RST pin low and hold the CIP- reset state (see Figure 25.2). When level above V ...
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C8051F70x/71x SFR Definition 25.1. VDM0CN: V Bit 7 6 Name VDMEN VDDSTAT Type R/W R Reset Varies Varies SFR Address = 0xFF; SFR Page = All Pages Bit Name 7 VDMEN V Monitor Enable. DD This bit turns the V ...
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Comparator0 Reset Comparator0 can be configured as a reset source by writing the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on the ...
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C8051F70x/71x SFR Definition 25.2. RSTSRC: Reset Source Bit 7 6 FERROR C0RSEF Name R R Type 0 Varies Reset SFR Address = 0xEF; SFR Page = All Pages Bit Name Description 7 Unused Unused. 6 FERROR Flash Error Reset Flag. ...
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Watchdog Timer The MCU includes a programmable Watchdog Timer (WDT) running off the system clock. A WDT overflow will force the MCU into the reset state. To prevent the reset, the WDT must be restarted by application soft- ware ...
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C8051F70x/71x SFR Definition 26.1. WDTCN: Watchdog Timer Control Bit 7 6 Name Type 0 0 Reset SFR Address = 0xE3; SFR Page = All Pages Bit Name Description 7:0 WDT[7:0] WDT Control. 4 WDTSTATUS Watchdog Status Bit. 2:0 WDTTIMEOUT Watchdog ...
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Oscillators and Clock Selection C8051F70x/71x devices include a programmable internal high-frequency oscillator and an external oscilla- tor drive circuit. The internal high-frequency oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 27.1. ...
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C8051F70x/71x SFR Definition 27.1. CLKSEL: Clock Select Bit 7 6 Name CLKRDY CLKDIV[2:0] Type R R/W Reset 0 0 SFR Address = 0xBD; SFR Page= F Bit Name 7 CLKRDY System Clock Divider Clock Ready Flag. 0: The selected clock ...
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Programmable Internal High-Frequency (H-F) Oscillator All C8051F70x/71x devices include a programmable internal high-frequency oscillator that defaults as the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register as defined by SFR ...
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C8051F70x/71x SFR Definition 27.3. OSCICN: Internal H-F Oscillator Control Bit 7 6 IOSCEN IFRDY SUSPEND Name R/W R Type 1 1 Reset SFR Address = 0xA9; SFR Page = F Bit Name 7 IOSCEN Internal H-F Oscillator Enable Bit. 0: ...
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External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys- tal/resonator must ...
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C8051F70x/71x SFR Definition 27.4. OSCXCN: External Oscillator Control Bit 7 6 XTLVLD XOSCMD[2:0] Name R Type 0 0 Reset SFR Address = 0xB5; SFR Page = F Bit Name 7 XTLVLD Crystal Oscillator Valid Flag. (Read only when XOSCMD = ...
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External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 27.1, Option 1. The External Oscillator Frequency Control value (XFCN) should ...
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C8051F70x/71x 32.768 kHz 22pF* * Capacitor values depend on crystal specifications Figure 27.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 27.3.2. External RC Example network is used as an external oscillator source for the MCU, the ...
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External Capacitor Example If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in Figure 27.1, Option 3. The capacitor should be no greater than 100 pF; however for very ...
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C8051F70x/71x 28. Port Input/Output Digital and analog resources are available through 64 I/O pins. Each of the Port pins P0.0–P2.7 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources, or assigned to an analog ...
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Port I/O Modes of Operation Port pins P0.0 - P6.5 use the Port I/O cell shown in Figure 28.2. Each Port I/O cell can be configured by software for analog I/O or digital I/O using the PnMDIN registers. On ...
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C8051F70x/71x 28.1.3. Interfacing Port I Logic All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at a supply voltage higher than VDD and less than 5.25 ...
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Table 28.1. Port I/O Assignment for Analog Functions Analog Function ADC Input Comparator0 Input CS0 Input Voltage Reference (VREF0) Ground Reference (AGND) External Oscillator in Crystal Mode (XTAL1) External Oscillator in RC Crystal Mode (XTAL2) C8051F70x/71x Potentially Assignable ...
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C8051F70x/71x 28.2.2. Assigning Port I/O Pins to Digital Functions Any Port pins not assigned to analog functions may be assigned to digital functions or used as GPIO. Most digital functions rely on the Crossbar for pin assignment; however, some digital ...
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Priority Crossbar Decoder The Priority Crossbar Decoder assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (exclud- ing UART0, ...
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C8051F70x/71x Port P0 Pin Number Special Function Signals TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A SYSCLK CEX0 CEX1 CEX2 ECI ...
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Port P0 Pin Number Special Function Signals TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A SYSCLK CEX0 CEX1 CEX2 ECI ...
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C8051F70x/71x Port P0 Pin Number Special Function Signals TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A SYSCLK CEX0 CEX1 CEX2 ECI ...
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... Port I/O (in input mode), regardless of the XBRn Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode Table alternative, the Configuration Wizard utility of the Silicon Labs IDE software will determine the Port I/O pin-assignments based on the XBRn Register settings. ...
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C8051F70x/71x SFR Definition 28.1. XBR0: Port I/O Crossbar Register 0 Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xE1; SFR Page = F Bit Name 7:6 Unused Read = 00b; Write = Don’t Care. 5 ...
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SFR Definition 28.2. XBR1: Port I/O Crossbar Register 1 Bit 7 6 Name WEAKPUD XBARE R/W R/W Type 0 0 Reset SFR Address = 0xE2; SFR Page = F Bit Name 7 WEAKPUD Port I/O Weak Pullup Disable. 0: Weak ...
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C8051F70x/71x 28.5. Port Match Port match functionality allows system events to be triggered by a logic value change P1. A soft- ware controlled value stored in the PnMATCH registers specifies the expected or normal logic values of ...
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SFR Definition 28.4. P0MAT: Port 0 Match Register Bit 7 6 Name Type 1 1 Reset SFR Address = 0xF3; SFR Page = 0 Bit Name 7:0 P0MAT[7:0] Port 0 Match Value. Match comparison value used on Port 0 for ...
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C8051F70x/71x SFR Definition 28.6. P1MAT: Port 1 Match Register Bit 7 6 Name Type 1 1 Reset SFR Address = 0xE1; SFR Page = 0 Bit Name 7:0 P1MAT[7:0] Port 1 Match Value. Match comparison value used on Port 1 ...
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SFR Definition 28.7. P0: Port 0 Bit 7 6 Name Type 1 1 Reset SFR Address = 0x80; SFR Page = All Pages; Bit Addressable Bit Name Description 7:0 P0[7:0] Port 0 Data. Sets the Port latch logic value or ...
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C8051F70x/71x SFR Definition 28.9. P0MDOUT: Port 0 Output Mode Bit 7 6 Name Type 0 0 Reset SFR Address = 0xA4; SFR Page = F Bit Name 7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively). These bits are ignored if ...
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SFR Definition 28.11. P0DRV: Port 0 Drive Strength Bit 7 6 Name Type 0 0 Reset SFR Address = 0xF9; SFR Page = F Bit Name 7:0 P0DRV[7:0] Drive Strength Configuration Bits for P0.7–P0.0 (respectively). Configures digital I/O Port cells ...
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C8051F70x/71x SFR Definition 28.13. P1MDIN: Port 1 Input Mode Bit 7 6 Name Type 1* 1 Reset SFR Address = 0xF2; SFR Page = F Bit Name 7:0 P1MDIN[7:0] Analog Configuration Bits for P1.7–P1.0 (respectively). Port pins configured for analog ...
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SFR Definition 28.15. P1SKIP: Port 1 Skip Bit 7 6 Name Type 0 0 Reset SFR Address = 0xD5; SFR Page = F Bit Name 7:0 P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits. These bits select Port 1 pins to ...
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C8051F70x/71x SFR Definition 28.17. P2: Port 2 Bit 7 6 Name Type 1 1 Reset SFR Address = 0xA0; SFR Page = All Pages; Bit Addressable Bit Name Description 7:0 P2[7:0] Port 2 Data. Sets the Port latch logic value ...