C8051F997-GUR Silicon Labs, C8051F997-GUR Datasheet
C8051F997-GUR
Specifications of C8051F997-GUR
Related parts for C8051F997-GUR
C8051F997-GUR Summary of contents
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Ultra Low Power Consumption - 150 µA/MHz in active mode (24.5 MHz clock µs wakeup time - 10 nA sleep mode with memory retention - 50 nA sleep mode with brownout detector - 300 nA sleep mode with ...
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C8051F99x-C8051F98x Table of Contents 1. System Overview.................................................................................................... 17 1.1. CIP-51™ Microcontroller Core.......................................................................... 25 1.1.1. Fully 8051 Compatible.............................................................................. 25 1.1.2. Improved Throughput ............................................................................... 25 1.1.3. Additional Features .................................................................................. 25 1.2. Port Input/Output............................................................................................... 26 1.3. Serial Ports ....................................................................................................... 27 1.4. Programmable Counter ...
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IREF0 Specifications......................................................................................... 90 7. Comparator ............................................................................................................. 91 7.1. Comparator Inputs ............................................................................................ 91 7.2. Comparator Outputs ......................................................................................... 92 7.3. Comparator Response Time............................................................................. 92 7.4. Comparator Hysteresis ..................................................................................... 92 7.5. Comparator Register Descriptions.................................................................... 93 7.6. Comparator0 Analog Multiplexer ...................................................................... 96 8. ...
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C8051F99x-C8051F98x 13.4.Interrupt Latency............................................................................................. 138 13.5.Interrupt Register Descriptions ....................................................................... 140 13.6.External Interrupts INT0 and INT1.................................................................. 147 14. Flash Memory ....................................................................................................... 149 14.1.Programming the Flash Memory .................................................................... 149 14.1.1.Flash Lock and Key Functions ............................................................... 149 14.1.2.Flash Erase Procedure .......................................................................... 150 14.1.3.Flash Write ...
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Power Internal Oscillator......................................................................... 187 19.3.External Oscillator Drive Circuit...................................................................... 187 19.3.1.External Crystal Mode............................................................................ 187 19.3.2.External RC Mode.................................................................................. 189 19.3.3.External Capacitor Mode........................................................................ 190 19.3.4.External CMOS Clock Mode .................................................................. 190 19.4.Special Function Registers for Selecting and Configuring the System Clock 191 20. ...
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C8051F99x-C8051F98x 22.3.SMBus Operation ........................................................................................... 235 22.3.1.Transmitter vs. Receiver ........................................................................ 235 22.3.2.Arbitration............................................................................................... 235 22.3.3.Clock Low Extension.............................................................................. 236 22.3.4.SCL Low Timeout................................................................................... 236 22.3.5.SCL High (SMBus Free) Timeout .......................................................... 236 22.4.Using the SMBus............................................................................................ 237 22.4.1.SMBus Configuration Register............................................................... 238 22.4.2.SMB0CN Control Register ..................................................................... 241 ...
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Timer with Auto-Reload................................................................ 292 25.3.2.8-Bit Timers with Auto-Reload ............................................................... 293 25.3.3.SmaRTClock/External Oscillator Capture Mode .................................... 294 26. Programmable Counter Array ............................................................................. 298 26.1.PCA Counter/Timer ........................................................................................ 299 26.2.PCA0 Interrupt Sources.................................................................................. 300 26.3.Capture/Compare Modules ............................................................................ 301 26.3.1.Edge-triggered Capture Mode................................................................ 302 26.3.2.Software ...
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... Figure 1.8. C8051F988 Block Diagram .................................................................... 21 Figure 1.9. C8051F989 Block Diagram .................................................................... 22 Figure 1.10. C8051F990 Block Diagram .................................................................. 22 Figure 1.11. C8051F991 Block Diagram .................................................................. 23 Figure 1.12. C8051F996 Block Diagram .................................................................. 23 Figure 1.13. C8051F997 Block Diagram .................................................................. 24 Figure 1.14. Port I/O Functional Block Diagram ....................................................... 26 Figure 1.15. PCA Block Diagram.............................................................................. 27 Figure 1.16. ADC0 Functional Block Diagram.......................................................... 28 Figure 1.17. ADC0 Multiplexer Block Diagram ......................................................... 29 Figure 1 ...
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Figure 7.3. CP0 Multiplexer Block Diagram.............................................................. 96 Figure 8.1. CS0 Block Diagram ................................................................................ 98 Figure 8.2. Auto-Scan Example.............................................................................. 101 Figure 8.3. CS0 Multiplexer Block Diagram............................................................ 116 Figure 9.1. CIP-51 Block Diagram.......................................................................... 118 Figure 10.1. C8051F99x-C8051F98x Memory Map ............................................... 127 Figure ...
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C8051F99x-C8051F98x Figure 24.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 268 Figure 24.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 269 Figure 24.8. SPI Master Timing (CKPHA = 0)........................................................ 273 Figure 24.9. SPI Master Timing (CKPHA = 1)........................................................ ...
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List of Tables Table 2.1. Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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C8051F99x-C8051F98x Table 22.1. SMBus Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Table 22.2. Minimum ...
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List of Registers SFR Definition 5.1. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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C8051F99x-C8051F98x SFR Definition 13.2. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SFR Definition 21.9. P0SKIP: Port0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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C8051F99x-C8051F98x SFR Definition 26.6. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . . 315 SFR Definition 26.7. PCA0CPLn: PCA Capture Module Low Byte . . ...
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... User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands ...
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C8051F99x-C8051F98x CIP-51 8051 Power On Controller Core Reset/PMU 8 kB ISP Flash Wake Program Memory Reset 256 Byte SRAM C2CK/RST Debug / Programming 256 Byte XRAM Hardware C2D VDD VREG Digital Power Precision 24.5 MHz Oscillator Low Power GND 20 ...
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CIP-51 8051 Power On Controller Core Reset/PMU 4 kB ISP Flash Wake Program Memory Reset 256 Byte SRAM C2CK/RST Debug / Programming 256 Byte XRAM Hardware C2D CRC Engine VDD VREG Digital SYSCLK Power Precision 24.5 MHz Oscillator Low Power ...
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C8051F99x-C8051F98x CIP-51 8051 Power On Controller Core Reset/PMU 2 kB ISP Flash Wake Program Memory Reset 256 Byte SRAM Debug / C2CK/RST Programming 256 Byte XRAM Hardware C2D VDD VREG Digital Power Precision 24.5 MHz Oscillator Low Power 20 MHz ...
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CIP-51 8051 Power On Controller Core Reset/PMU 8 kB ISP Flash Wake Program Memory Reset 256 Byte SRAM C2CK/RST Debug / Programming 256 Byte XRAM Hardware C2D CRC Engine VDD VREG Digital SYSCLK Power Precision 24.5 MHz Oscillator Low Power ...
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C8051F99x-C8051F98x CIP-51 8051 Power On Controller Core Reset/PMU 4 kB ISP Flash Wake Program Memory Reset 256 Byte SRAM C2CK/RST Debug / Programming Hardware C2D VDD VREG Digital Power Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator GND External ...
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CIP-51 8051 Power On Controller Core Reset/PMU 8 kB ISP Flash Wake Program Memory Reset 256 Byte SRAM C2CK/RST Debug / Programming 256 Byte XRAM Hardware C2D CRC Engine VDD VREG Digital SYSCLK Power Precision 24.5 MHz Oscillator Low Power ...
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... MHz Oscillator Low Power 20 MHz Oscillator GND External XTAL1 Oscillator XTAL2 Circuit XTAL3 SmaRTClock Oscillator XTAL4 System Clock Configuration Figure 1.13. C8051F997 Block Diagram 24 Port I/O Configuration Digital Peripherals UART Timers Priority Crossbar PCA/ Decoder WDT CRC SMBus Engine SPI SYSCLK ...
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... CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F99x-C8051F98x family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052. ...
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C8051F99x-C8051F98x 1.2. Port Input/Output Digital and analog resources are available through I/O pins. Port pins are organized as three byte- wide ports. Port pins P0.0–P1.7 can be defined as digital or analog I/O. Digital I/O pins can ...
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Serial Ports The C8051F99x-C8051F98x Family includes an SMBus/I baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU ...
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C8051F99x-C8051F98x 1.5. SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode C8051F99x-C8051F98x devices have a 300 ksps, 10-bit or 75 ksps 12-bit successive-approximation- register (SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an ...
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P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.2 P1.3 *P1.4 Temp Sensor Digital Supply VDD *Only available on 24-pin devices. Figure 1.17. ADC0 Multiplexer Block Diagram 1.6. Programmable Current Reference (IREF0) C8051F99x-C8051F98x devices include an on-chip programmable current reference (source ...
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C8051F99x-C8051F98x CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 Analog Input Multiplexer Px.x CP0 + Px.x Px.x CP0 - Px.x Figure 1.18. Comparator 0 Functional Block Diagram 30 VDD CPT0MD CP0 Rising-edge Interrupt + SET SET ...
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... C8051F989- 512 C8051F989- 512 C8051F990- 512 C8051F991- 512 C8051F996- 512 C8051F996- 512 C8051F997- 512 C8051F997- 512 C8051F99x-C8051F98x 12-bit — — — — 10-bit — ...
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C8051F99x-C8051F98x 3. Pinout and Package Definitions Table 3.1. Pin Definitions for the C8051F99x-C8051F98x Pin Numbers ‘F980/1/2 ‘F986/7 ‘F986/7 Name ‘F983/5 ‘F988/9 ‘F988/9 ‘F990/1 ‘F996/7 ‘F996/7 -GM -GM - GND RST/ 5 ...
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Table 3.1. Pin Definitions for the C8051F99x-C8051F98x (Continued) Pin Numbers ‘F980/1/2 ‘F986/7 ‘F986/7 Name ‘F983/5 ‘F988/9 ‘F988/9 ‘F990/1 ‘F996/7 ‘F996/7 -GM -GM -GU P0. AGND* P0. XTAL1/ RTCOUT P0. XTAL2/ WAKEOUT ...
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C8051F99x-C8051F98x Table 3.1. Pin Definitions for the C8051F99x-C8051F98x (Continued) Pin Numbers ‘F980/1/2 ‘F986/7 ‘F986/7 Name ‘F983/5 ‘F988/9 ‘F988/9 ‘F990/1 ‘F996/7 ‘F996/7 -GM -GM -GU P0. CNVSTR* P0. IREF0 P1 CP0+ P1.1 ...
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P0.0/VREF* C8051F980/1/2/3/5 C8051F990/1 -GM 3 GND Top View 4 VDD GND (Optional Connection) 5 RST/C2CK 6 *Note: Signal only available on ‘F980, ‘F982 and ‘F990 devices. Figure 3.1. QFN-20 Pinout Diagram (Top View) C8051F99x-C8051F98x 16 15 P0.7/IREF0 14 ...
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C8051F99x-C8051F98x N.C. 1 GND 2 VDD 3 N.C. 4 N.C. 5 RST/C2CK 6 *Note: Signal only available on ‘F986, ‘F988, and ‘F996 devices. Figure 3.2. QFN-24 Pinout Diagram (Top View) 36 C8051F986/7/8/9 C8051F996/7 -GM Top View GND (optional connection) Rev. ...
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P0.2/XTAL1/RTCOUT 1 P0.1/AGND P0.0/VREF* 4 N.C. GND 5 VDD 6 N. N.C. 9 RST/C2CK 10 P2.7/C2D 11 P1.7/XTAL4 12 P1.6/XTAL3 *Note: Signal only available on ‘F986, ‘F988, and ‘F996 devices. Figure 3.3. QSOP-24 Pinout Diagram (Top ...
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C8051F99x-C8051F98x Figure 3.4. QFN-20 Package Drawing Table 3.2. QFN-20 Package Dimensions Dimension Min Typ A 0.50 0.55 A1 0.00 0.02 b 0.20 0.25 c 0.27 0.32 D 3.00 BSC D2 1.65 1.70 e 0.50 BSC E 3.00 BSC E2 ...
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Figure 3.5. Typical QFN-20 Landing Diagram C8051F99x-C8051F98x Rev. 1.1 39 ...
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C8051F99x-C8051F98x Dimension Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This ...
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Figure 3.6. QFN-24 Package Drawing Table 3.4. QFN-24 Package Dimensions Dimension Min Typ Max A 0.70 0.75 0.80 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D 4.00 BSC D2 2.55 2.70 2.80 e 0.50 BSC E 4.00 BSC E2 ...
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C8051F99x-C8051F98x Figure 3.7. Typical QFN-24 Landing Diagram 42 Rev. 1.1 ...
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Table 3.5. PCB Land Pattern Dimension MIN C1 3. 0.20 X2 2.70 Y1 0.65 Y2 2.70 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based ...
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C8051F99x-C8051F98x Figure 3.8. QSOP-24 Package Diagram Table 3.6. QSOP-24 Package Dimensions Dimension Min Typ A — — A1 0.10 — b 0.20 — c 0.10 — D 8.65 BSC. E 6.00 BSC E1 3.90 BSC e 0.635 BSC Notes: 1. ...
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Figure 3.9. QSOP-24 Landing Diagram Table 3.7. PCB Land Pattern Dimension Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. ...
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C8051F99x-C8051F98x 4. Electrical Characteristics Throughout the Electrical Characteristics chapter, “VDD” refers to the Supply Voltage. 4.1. Absolute Maximum Specifications Table 4.1. Absolute Maximum Ratings Parameter Ambient Temperature under Bias Storage Temperature Voltage on any Port I/O Pin or RST with ...
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Electrical Characteristics Table 4.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in ...
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C8051F99x-C8051F98x Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this ...
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Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. ...
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C8051F99x-C8051F98x 4200 F < 14 MHz 4100 Oneshot Enabled 4000 3900 3800 3700 3600 3500 3400 3300 3200 3100 3000 2900 2800 2700 2600 2500 2400 2300 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 ...
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4200 4100 4000 3900 3800 3700 3600 3500 3400 3300 3200 3100 3000 2900 2800 2700 2600 2500 2400 2300 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 ...
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C8051F99x-C8051F98x Table 4.3. Port I/O DC Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters Output High Voltage High Drive Strength, PnDRV IOH = –3 mA, Port I/O push-pull IOH ...
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C8051F99x-C8051F98x Typical VOH (High Drive Mode) 3.6 3.3 3 2.7 2.4 2.1 1.8 1.5 1.2 0 Load Current (mA) Typical VOH (Low Drive Mode) 3.6 3.3 3 2.7 2.4 2.1 1.8 1.5 1.2 ...
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C8051F99x-C8051F98x 1.8 1.5 1.2 0.9 0.6 0.3 0 -80 -70 1.8 1.5 1.2 0.9 0.6 0 Figure 4.4. Typical VOL Curves, 1.8–3 Typical VOL (High Drive Mode) VDD = 3.6V VDD = 3.0V VDD ...
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Table 4.4. Reset Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameter RST Output Low Voltage RST Input High Voltage RST Input Low Voltage RST Input Pullup Current VDD Monitor Threshold (V ...
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C8051F99x-C8051F98x Table 4.5. Power Management Electrical Specifications V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameter Idle Mode Wake-up Time Suspend Mode Wake-up Time Low Power or Precision Osc. Sleep Mode Wake-up Time Table ...
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Table 4.9. SmaRTClock Characteristics V = 1 –40 to +85 °C unless otherwise specified; Using factory-calibrated settings Parameter Oscillator Frequency (LFO) Table 4.10. ADC0 Electrical Characteristics V = 1.8 to 3.6 V, VREF ...
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C8051F99x-C8051F98x Table 4.10. ADC0 Electrical Characteristics (Continued 1.8 to 3.6 V, VREF = 1.65 V (REFSL[1:0] = 11), DD Parameter Analog Inputs ADC Input Voltage Range Absolute Pin Voltage with respect to GND Sampling Capacitance Input Multiplexer Impedance ...
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Table 4.12. Voltage Reference Electrical Characteristics V – = 1 +85 °C unless otherwise specified. DD Parameter Internal High-Speed Reference (REFSL[1:0] = 11) Output Voltage VREF Turn-on Time Supply Current External Reference (REFSL[1:0] = 00, ...
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C8051F99x-C8051F98x Table 4.13. IREF0 Electrical Characteristics V – = 1 +85 °C, unless otherwise specified. DD Parameter Static Performance Resolution High Current Mode, Source Output Compliance Range Integral Nonlinearity Differential Nonlinearity Offset Error High Current ...
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Table 4.14. Comparator Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise noted. DD Parameter Response Time: * Mode 2 1 Response Time: * Mode 1, ...
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C8051F99x-C8051F98x Table 4.14. Comparator Electrical Characteristics (Continued 1.8 to 3.6 V, –40 to +85 °C unless otherwise noted. DD Parameter Hysteresis Mode 0 Hysteresis 1 Hysteresis 2 Hysteresis 3 Hysteresis 4 Mode 1 Hysteresis 1 Hysteresis 2 Hysteresis ...
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Table 4.16. Capacitive Sense Electrical Characteristics V = 1 –40 to +85 °C unless otherwise specified Parameter 1 Single Conversion Time Number of Channels Capacitance per Code Maximum External Capacitive Load Maximum ...
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C8051F99x-C8051F98x 5. SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode The ADC0 on C8051F980/6 and C8051F990/6 devices is a 300 ksps, 10-bit or 75 ksps, 12-bit successive- approximation-register (SAR) ADC with integrated track-and-hold and programmable window ...
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Output Code Formatting The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the setting of ...
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C8051F99x-C8051F98x 5.2. Modes of Operation ADC0 has a maximum conversion speed of 300 ksps in 10-bit mode. The ADC0 conversion clock (SARCLK divided version of the system clock when burst mode is disabled (BURSTEN = 0 ...
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Tracking Modes Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to be accurate. The minimum tracking time is given in Table 4.10. The AD0TM bit in register ADC0CN controls the ...
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C8051F99x-C8051F98x 5.2.3. Burst Mode Burst Mode is a power saving feature that allows ADC0 to remain in a low power state between conversions. When Burst Mode is enabled, ADC0 wakes from a low power state, accumulates 16, ...
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Settling Time Requirements A minimum amount of tracking time is required before each conversion can be performed, to allow the sampling capacitor voltage to settle. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any ...
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C8051F99x-C8051F98x 5.2.5. Gain Setting The ADC has gain settings of 1x and 0.5x mode, the full scale reading of the ADC is determined directly 0.5x mode, the full-scale reading of the ADC occurs when ...
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Table 5.1. Representative Conversion Times and Energy Consumption for the SAR ADC with 1.65 V High-Speed VREF Normal Power Mode 8 bit 8.17 MHz Highest nominal (24.5/3) SAR clock frequency 11 Total number of conversion clocks required 1.5 µs Total ...
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C8051F99x-C8051F98x SFR Definition 5.1. ADC0CN: ADC0 Control Bit 7 6 Name AD0EN BURSTEN AD0INT R/W R/W Type Reset 0 0 SFR Page = 0x0; SFR Address = 0xE8; bit-addressable; Bit Name 7 AD0EN ADC0 Enable. 0: ADC0 Disabled (low-power shutdown). ...
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SFR Definition 5.2. ADC0CF: ADC0 Configuration Bit 7 6 Name AD0SC[4:0] Type Reset 1 1 SFR Page = 0x0; SFR Address = 0x97 Bit Name 7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Divider. SAR Conversion clock is derived from FCLK by ...
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C8051F99x-C8051F98x SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration Bit 7 6 Name AD012BE AD0AE R/W W Type Reset 0 0 SFR Page = 0x0; SFR Address = 0xBA Bit Name 7 AD012BE ADC0 12-Bit Mode Enable. Enables 12-bit Mode on ...
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SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time Bit 7 6 Name AD0LPM Type R Reset SFR Page = All; SFR Address = 0xBB Bit Name 7 AD0LPM ADC0 Low Power Mode Enable. Enables Low Power ...
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C8051F99x-C8051F98x SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time Bit 7 6 Name Reserved Type Reset SFR Page = All; SFR Address = 0xBC Bit Name 7 Reserved Read = 0b; Write = Must Write ...
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SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte Bit 7 6 Name Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xBE Bit Name Description 7:0 ADC0[15:8] ADC0 Data Word High Byte. Note: If Accumulator shifting is ...
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C8051F99x-C8051F98x 5.6. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user- programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code ...
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SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte Bit 7 6 Name Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xC6 Bit Name 7:0 AD0LT[15:8] ADC0 Less-Than High Byte. Most Significant Byte of the 16-bit Less-Than window ...
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C8051F99x-C8051F98x 5.6.1. Window Detector In Single-Ended Mode Figure 5.5 shows two example ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can range from 0 to VREF x (1023/1024) with respect to GND, and is represented by ...
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ADC0 Analog Multiplexer ADC0 on C8051F99x-C8051F98x has an analog multiplexer, referred to as AMUX0. AMUX0 selects the positive inputs to the single-ended ADC0. Any of the following may be selected as the positive input: Port I/O pins, the on-chip ...
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C8051F99x-C8051F98x SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select Bit 7 6 Name R R Type 0 0 Reset SFR Page = 0x0; SFR Address = 0x96 Bit Name 7:5 Unused Read = 000b; Write = Don’t Care. 4:0 AD0MX ...
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Temperature Sensor An on-chip temperature sensor is included on the C8051F99x-C8051F98x which can be directly accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the temperature sensor, the ADC mux channel should select the ...
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C8051F99x-C8051F98x 5.8.1. Calibration The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature mea- surements (see Table 4.11 for linearity specifications). For absolute temperature measurements, offset and/or gain calibration is recommended. Typically a 1-point (offset) calibration includes ...
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SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte Bit 7 6 Name R R Type Varies Varies Varies Reset SFR Page = 0xF; SFR Address = 0x8E Bit Name 7:0 TOFF[9:2] Temperature Sensor Offset High Bits. Most Significant Bits ...
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C8051F99x-C8051F98x 5.9. Voltage and Ground Reference Options The voltage reference MUX is configurable to use an externally connected voltage reference, the internal voltage reference, or one of two power supply voltages (see Figure 5.10). The ground reference MUX allows the ...
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External Voltage Reference To use an external voltage reference, REFSL[1:0] should be set to 00. Bypass capacitors should be added as recommended by the manufacturer of the external voltage reference. If the manufacturer does not pro- vide recommendations, a ...
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C8051F99x-C8051F98x SFR Definition 5.15. REF0CN: Voltage Reference Control Bit 7 6 Name REFGND R R Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xD3 Bit Name 7:6 Unused Read = 00b; Write = Don’t Care. 5 REFGND ...
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Programmable Current Reference (IREF0) C8051F99x-C8051F98x devices include an on-chip programmable current reference (source or sink) with two output current settings: Low Power Mode and High Current Mode. The maximum current output in Low Power Mode is 63 µA (1 ...
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C8051F99x-C8051F98x SFR Definition 6.2. IREF0CF: Current Reference Configuration Bit 7 6 Name PWMEN Type R/W R/W Reset 0 0 SFR Page = All; SFR Address = 0xB9 Bit Name 7 PWMEN PWM Enhanced Mode Enable. Enables the PWM Enhanced Mode. ...
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Comparator C8051F99x-C8051F98x devices include an on-chip programmable voltage comparator: Comparator 0 (CPT0) shown in Figure 7.1. The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: ...
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C8051F99x-C8051F98x 7.2. Comparator Outputs When a comparator is enabled, its output is a logic 1 if the voltage at the positive input is higher than the voltage at the negative input. When disabled, the comparator output is a logic 0. ...
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CP0+ VIN+ + CP0 CP0- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS VIN OUTPUT V OL Positive Hysteresis Disabled Figure 7.2. Comparator Hysteresis Plot 7.5. Comparator Register Descriptions The SFRs used to ...
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C8051F99x-C8051F98x SFR Definition 7.1. CPT0CN: Comparator 0 Control Bit 7 6 Name CP0EN CP0OUT CP0RIF Type R/W R Reset 0 0 SFR Page= 0x0; SFR Address = 0x9B Bit Name 7 CP0EN Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 ...
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SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection Bit 7 6 Name CP0RIE Type R/W R Reset 1 0 SFR Page = 0x0; SFR Address = 0x9D Bit Name 7 Reserved Read = 1b, Must Write 1b. 6 Unused Read ...
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C8051F99x-C8051F98x 7.6. Comparator0 Analog Multiplexer Comparator0 C8051F99x-C8051F98x devices has an analog input multiplexer to connect Port I/O pins and internal signals the comparator inputs; CP0+/CP0- are the positive and negative input multiplexers for Comparator0. The comparator input multiplexers directly support ...
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SFR Definition 7.3. CPT0MX: Comparator0 Input Channel Select Bit 7 6 Name CMX0N[3:0] R/W R/W Type 0 1 Reset SFR Page = 0x0; SFR Address = 0x9F Bit Name 7:4 CMX0N Comparator0 Negative Input Selection. Selects the negative input channel ...
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C8051F99x-C8051F98x 8. Capacitive Sense (CS0) The Capacitive Sense subsystem uses a capacitance-to-digital circuit to determine the capacitance on a port pin. The module can take measurements from different port pins using the module’s analog multiplexer. The module is enabled only ...
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Configuring Port Pins as Capacitive Sense Inputs In order for a port pin to be measured by CS0, that port pin must be configured as an analog input (see “21. Port Input/Output” ). Configuring the input multiplexer to a ...
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C8051F99x-C8051F98x 8.4. CS0 Multiple Channel Enable CS0 has the capability of measuring the total capacitance of multiple channels using a single conversion. When the multiple channel feature is enabled (CS0MCEN = 1), Channels selected by CS0SCAN0/1 are internally shorted together ...
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Automatic Scanning (Method 1—CS0SMEN = 0) CS0 can be configured to automatically scan a sequence of contiguous CS0 input channels by configuring and enabling auto-scan. Using auto-scan with the CS0 comparator interrupt enabled allows a system to detect a ...
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C8051F99x-C8051F98x 8.9. Automatic Scanning (Method 2—CS0SMEN = 1) When CS0SMEN is enabled, CS0 uses an alternate autoscanning method that uses the contents of CS0SCAN0 and CS0SCAN1 to determine which channels to include in the scan. This maximizes flexibility for application ...
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CS0 Conversion Accumulator CS0 can be configured to accumulate multiple conversions on an input channel. The number of samples to be accumulated is configured using the CS0ACU2:0 bits (CS0CF2:0). The accumulator can accumulate 16, 32, or ...
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C8051F99x-C8051F98x 8.12. CS0 Pin Monitor The CS0 module provides accurate conversions in all operating modes of the CPU, peripherals and I/O ports. Pin monitoring circuits are provided to improve interference immunity from high-current output pin switching. The CS0 Pin Monitor ...
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Adjusting CS0 For Special Situations There are several configuration options in the CS0 module designed to modify the operation of the circuit and address special situations. In particular, any circuit with more than 500 ohms of series impedance between ...
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C8051F99x-C8051F98x SFR Definition 8.1. CS0CN: Capacitive Sense Control Bit 7 6 Name CS0EN CS0EOS CS0INT Type R/W R Reset 0 0 SFR Page = 0x0; SFR Address = 0xB0 Bit Name 7 CS0EN CS0 Enable. 0: CS0 disabled and in ...
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SFR Definition 8.2. CS0CF: Capacitive Sense Configuration Bit 7 6 Name CS0SMEN CS0CM[2:0] Type R/W R/W Reset 0 0 SFR Page = 0x0; SFR Address = 0xAA Bit Name 7 CS0SMEN CS0 Channel Scan Masking Enable. 0: The CS0SCAN0 and ...
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C8051F99x-C8051F98x SFR Definition 8.3. CS0DH: Capacitive Sense Data High Byte Bit 7 6 Name Type R R Reset 0 0 SFR Page = 0x0; SFR Address = 0xEE Bit Name 7:0 CS0DH CS0 Data High Byte. Stores the high byte ...
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SFR Definition 8.5. CS0SCAN0: Capacitive Sense Channel Scan Mask 0 Bit 7 6 Name Type R/W R/W Reset 0 0 SFR Page = 0x0; SFR Address = 0xDD Bit Name 7:0 CS0SCAN[7:0] Capacitive Sense Channel Scan Mask for Port 0. ...
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C8051F99x-C8051F98x SFR Definition 8.7. CS0SS: Capacitive Sense Auto-Scan Start Channel Bit 7 6 Name Type R R Reset 0 0 SFR Page = 0x0; SFR Address = 0xDD Bit Name 7:5 Unused Read = 000b; Write = Don’t care 4:0 ...
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SFR Definition 8.9. CS0THH: Capacitive Sense Comparator Threshold High Byte Bit 7 6 Name Type R/W R/W Reset 0 0 SFR Page = 0x0; SFR Address = 0xFE Bit Name 7:0 CS0THH[7:0] CS0 Comparator Threshold High Byte. High byte of ...
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C8051F99x-C8051F98x SFR Definition 8.11. CS0MD1: Capacitive Sense Mode 1 Bit 7 6 Name Reserved CS0POL Type R/W Reset 0 0 SFR Page = 0x0; SFR Address = 0xAF Bit Name 7 Reserved Must write 0. 6 CS0POL CS0 Digital Comparator ...
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SFR Definition 8.12. CS0MD2: Capacitive Sense Mode 2 Bit 7 6 Name CS0CR[1:0] Type R/W Reset 0 1 SFR Page = 0x0; SFR Address = 0xF3 Bit Name 7:6 CS0CR[1:0] CS0 Conversion Rate. These bits control the conversion rate of ...
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C8051F99x-C8051F98x SFR Definition 8.13. CS0MD3: Capacitive Sense Mode 3 Bit 7 6 Name Type R/W R/W Reset 0 0 SFR Page = 0xF; SFR Address = 0xF3 Bit Name 7:5 Unused Read = 000b; Write = Don’t care 4:3 CS0RP[1:0] ...
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SFR Definition 8.14. CS0PM: Capacitive Sense Pin Monitor Bit 7 6 Name UAPM SPIPM SMBPM Type R/W R/W Reset 0 0 SFR Page = 0xF; SFR Address = 0xDE; Bit Name 7 UAPM UART Pin Monitor Enable. Enables monitoring of ...
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C8051F99x-C8051F98x 8.14. Capacitive Sense Multiplexer The input multiplexer can be controlled through two methods. The CS0MX register can be written to through firmware, or the register can be configured automatically using the modules auto-scan functionality (see “8.8. Automatic Scanning (Method ...
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SFR Definition 8.15. CS0MX: Capacitive Sense Mux Channel Select Bit 7 6 Name Reserved Reserved Reserved Type R/W R/W Reset 0 0 SFR Page = 0x0; SFR Address = 0xAB Bit Name 7:5 Reserved Read = 0000b; Write = 0000b. ...
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C8051F99x-C8051F98x 9. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset ...
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... This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or other on-chip resources. C2 details can be found in Section “27. C2 Interface” on page 317. The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs provides an integrated development environment (IDE) including editor, debugger and programmer. The IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-system device programming and debugging ...
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C8051F99x-C8051F98x Table 9.1. CIP-51 Instruction Set Summary Mnemonic ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to A ADDC A, ...
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Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic CLR A Clear A CPL A Complement Rotate A left RLC A Rotate A left through Carry RR A Rotate A right RRC A Rotate A right through Carry ...
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C8051F99x-C8051F98x Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic ANL C, /bit AND complement of direct bit to Carry ORL C, bit OR direct bit to carry ORL C, /bit OR complement of direct bit to Carry MOV C, bit ...
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Notes on Registers, Operands and Addressing Modes: Rn—Register R0–R7 of the currently selected register bank. @Ri—Data RAM location addressed indirectly through R0 or R1. rel—8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by ...
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C8051F99x-C8051F98x 9.4. CIP-51 Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in ...
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SFR Definition 9.3. SP: Stack Pointer Bit 7 6 Name Type Reset 0 0 SFR Page = All; SFR Address = 0x81 Bit Name 7:0 SP[7:0] Stack Pointer. The Stack Pointer holds the location of the top of the stack. ...
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C8051F99x-C8051F98x SFR Definition 9.6. PSW: Program Status Word Bit 7 6 Name CY AC Type R/W R/W Reset 0 0 SFR Page = All; SFR Address = 0xD0; Bit-Addressable Bit Name 7 CY Carry Flag. This bit is set when ...
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Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but ...
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C8051F99x-C8051F98x 10.1. Program Memory The CIP-51 core has program memory space. The C8051F99x-C8051F98x devices implement 8 kB (C8051F980/1/6/7, C8051F990/1/6/7 (C8051F982/3/8/9 (C8051F985) of this program memory space as in-system, re-programmable Flash memory, organized ...
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The addressing mode used by an instruction when accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR space. Instructions ...
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C8051F99x-C8051F98x 11. On-Chip XRAM The C8051F99x-C8051F98x MCUs include on-chip RAM mapped into the external data memory space (XRAM). The external memory space may be accessed using the external move instruction (MOVX) with the target address specified in either the data ...
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Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the C8051F99x-C8051F98x's resources and peripherals. The CIP-51 controller core duplicates the SFRs found ...
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C8051F99x-C8051F98x 12.1. SFR Paging To accommodate more than 128 SFRs in the 0x80 to 0xFF address space, SFR paging has been imple- mented. By default, all SFR accesses target SFR Page 0x0 to allow access to the registers listed in ...
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SFR Definition 12.1. SFR Page: SFR Page Bit 7 6 Name Type 0 0 Reset SFR Page = All; SFR Address = 0xA7 Bit Name 7:0 SFRPAGE[7:0] SFR Page. Specifies the SFR Page used when reading, writing, or modifying special ...
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C8051F99x-C8051F98x Table 12.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page CS0DH 0xEE 0x0 CS0DL 0xED 0x0 CS0MD1 0xAF 0x0 CS0MD2 0xF3 0x0 CS0MD3 0xF3 0xF CS0MX 0xAB ...
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Table 12.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page P1SKIP 0xD5 0x0 P2 0xA0 All P2DRV 0x9D 0xF P2MDOUT 0xA6 0x0 PCA0CN 0xD8 0x0 PCA0CPH0 0xFC 0x0 ...
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C8051F99x-C8051F98x Table 12.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page TCON 0x88 0x0 TH0 0x8C 0x0 TH1 0x8D 0x0 TL0 0x8A 0x0 TL1 0x8B 0x0 TMOD 0x89 ...
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Interrupt Handler The C8051F99x-C8051F98x microcontroller family includes an extended interrupt system supporting multiple interrupt sources and two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the ...
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C8051F99x-C8051F98x 13.3. Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be ...
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Table 13.1. Interrupt Summary Interrupt Priority Interrupt Source Vector Order 0x0000 Reset 0x0003 External Interrupt 0 (INT0) Timer 0 Overflow 0x000B 0x0013 External Interrupt 1 (INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B ...
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C8051F99x-C8051F98x 13.5. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described in the following register descriptions. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding ...
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SFR Definition 13.1. IE: Interrupt Enable Bit 7 6 Name EA ESPI0 Type R/W R/W Reset 0 0 SFR Page = All; SFR Address = 0xA8; Bit-Addressable Bit Name 7 EA Enable All Interrupts. Globally enables/disables all interrupts. It overrides ...
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C8051F99x-C8051F98x SFR Definition 13.2. IP: Interrupt Priority Bit 7 6 PSPI0 Name Type R R/W Reset 1 0 SFR Page = All; SFR Address = 0xB8; Bit-Addressable Bit Name 7 Unused Read = 1b, Write = don't care. 6 PSPI0 ...
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SFR Definition 13.3. EIE1: Extended Interrupt Enable 1 Bit 7 6 Name ET3 Type R/W R Reset 0 0 SFR Page = All; SFR Address = 0xE6 Bit Name 7 ET3 Enable Timer 3 Interrupt. This bit sets the masking ...
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C8051F99x-C8051F98x SFR Definition 13.4. EIP1: Extended Interrupt Priority 1 Bit 7 6 Name PT3 Type R/W R Reset 0 0 SFR Page = All; SFR Address = 0xF6 Bit Name 7 PT3 Timer 3 Interrupt Priority Control. This bit sets ...
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SFR Definition 13.5. EIE2: Extended Interrupt Enable 2 Bit 7 6 Name ECSEOS ECSDC R/W R/W Type Reset 0 0 SFR Page = All;SFR Address = 0xE7 Bit Name 7 Unused Read = 0b. Write = Don’t care. 6 ECSEOS ...
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C8051F99x-C8051F98x SFR Definition 13.6. EIP2: Extended Interrupt Priority 2 Bit 7 6 Name PCSEOS PCSDC R R/W Type Reset 0 0 SFR Page = All; SFR Address = 0xF7 Bit Name 7 Unused Read = 0b. Write = Don’t care. ...
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External Interrupts INT0 and INT1 The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high ...
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C8051F99x-C8051F98x SFR Definition 13.7. IT01CF: INT0/INT1 Configuration Bit 7 6 Name IN1PL IN1SL[2:0] Type R/W Reset 0 0 SFR Page = 0x0; SFR Address = 0xE4 Bit Name 7 IN1PL INT1 Polarity. 0: INT1 input is active low. 1: INT1 ...
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Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system through the C2 interface or by software using the MOVX write instruction. Once cleared to logic 0, ...
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C8051F99x-C8051F98x 14.1.2. Flash Erase Procedure The Flash memory is organized in 512-byte pages. The erase operation applies to an entire page (setting all bytes in the page to 0xFF). To erase an entire Flash page, perform the following steps: 1. ...
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Security Options The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft- ware as well as to prevent the viewing of proprietary program code and constants. The Program Store Write Enable (bit PSWE in ...
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C8051F99x-C8051F98x Table 14.1. Flash Security Summary Action Read, Write or Erase unlocked pages (except page with Lock Byte) Read, Write or Erase locked pages (except page with Lock Byte) Read or Write page containing Lock Byte (if no pages are ...
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... DEVICEID Special Function Register. The value of the DEVICEID register can be decoded as follows: 0xD0—C8051F990 0xD1—C8051F991 0xD6—C8051F996 0xD2—C8051F997 0xD3—C8051F980 0xD4—C8051F981 0xD5—C8051F982 0xD7—C8051F983 0xD8—C8051F985 ...
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C8051F99x-C8051F98x SFR Definition 14.2. REVID: Revision Identification Bit 7 6 Name Type 0 0 Reset SFR Page = 0x0F; SFR Address = 0xE2 Bit Name 7:0 REVID[7:0] Revision Identification. These bits contain a value that can be decoded to determine ...
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Flash Write and Erase Guidelines Any system which contains routines which write or erase Flash memory from software involves some risk that the write or erase routines will execute unintentionally if the CPU is operating outside its specified operating ...
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C8051F99x-C8051F98x 14.5.2. PSWE Maintenance 1. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set There should be exactly one routine in code that sets PSWE write ...
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Minimizing Flash Read Current The Flash memory in the C8051F99x-C8051F98x devices is responsible for a substantial portion of the total digital supply current when the device is executing code. Below are suggestions to minimize Flash read current. 1. Use ...
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C8051F99x-C8051F98x SFR Definition 14.3. PSCTL: Program Store R/W Control Bit 7 6 Name R R Type 0 0 Reset SFR Page =All; SFR Address = 0x8F Bit Name 7:2 Unused Read = 000000b, Write = don’t care. 1 PSEE Program ...
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SFR Definition 14.4. FLKEY: Flash Lock and Key Bit 7 6 Name Type 0 0 Reset SFR Page = All; SFR Address = 0xB7 Bit Name 7:0 FLKEY[7:0] Flash Lock and Key Register. Write: This register provides a lock and ...
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C8051F99x-C8051F98x SFR Definition 14.5. FLSCL: Flash Scale Bit 7 6 Name BYPASS Type R R/W Reset 0 0 SFR Page = All; SFR Address = 0xB7 Bit Name 7 Reserved Always Write BYPASS Flash Read Timing One-Shot ...
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Power Management C8051F99x-C8051F98x devices support 5 power modes: Normal, Idle, Stop, Suspend, and Sleep. The power management unit (PMU0) allows the device to enter and wake-up from the available power modes. A brief description of each power mode is ...
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C8051F99x-C8051F98x 15.1. Normal Mode The MCU is fully functional in normal mode. Figure 15.1 shows the on-chip power distribution to various peripherals. There are two supply voltages powering various sections of the chip: V nal core supply. All analog peripherals ...
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Idle Mode Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes execution. All internal registers and memory maintain their original ...
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C8051F99x-C8051F98x 15.4. Suspend Mode Setting the Suspend Mode Select bit (PMU0CF.6) causes the system clock to be gated off and all internal oscillators disabled. The system clock source must be set to the low power internal oscillator or the preci- ...
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The following wake-up sources can be configured to wake the device from sleep mode: SmaRTClock Oscillator Fail SmaRTClock Alarm Port Match Event Comparator0 Rising Edge The comparator requires a supply voltage of at least 1.8 V ...
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C8051F99x-C8051F98x SFR Definition 15.1. PMU0CF: Power Management Unit Configuration Bit 7 6 SLEEP SUSPEND CLEAR Name W W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xB5 Bit Name Description 7 SLEEP Sleep Mode Select 6 SUSPEND ...
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SFR Definition 15.2. PMU0FL: Power Management Unit Flag Bit 7 6 Name R R Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xCE Bit Name Description 7:1 Unused Unused 0 CS0WK CS0 Wake-up Source Enable and Flag ...
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C8051F99x-C8051F98x SFR Definition 15.3. PMU0MD: Power Management Unit Mode Bit 7 6 Name RTCOE WAKEOE MONDIS R/W R/W Type 0 0 Reset SFR Page = 0xF; SFR Address = 0xCE Bit Name 7 RTCOE Buffered SmaRTClock Output Enable. Enables the ...
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SFR Definition 15.4. PCON: Power Management Control Register Bit 7 6 Name Type 0 0 Reset SFR Page = All; SFR Address = 0x87 Bit Name Description 7:2 GF[5:0] General Purpose Flags 1 STOP Stop Mode Select 0 IDLE Idle ...
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C8051F99x-C8051F98x 16. Cyclic Redundancy Check Unit (CRC0) C8051F99x-C8051F98x devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a 16-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0 posts the ...
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The 16-bit C8051F99x-C8051F98x CRC algorithm can be described by the following code: unsigned short UpdateCRC (unsigned short CRC_acc, unsigned char CRC_input) { unsigned char i; #define POLY 0x1021 // Create the CRC "dividend" for polynomial arithmetic (binary arithmetic // with ...
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C8051F99x-C8051F98x 16.2. Preparing for a CRC Calculation To prepare CRC0 for a CRC calculation, software should set the initial value of the result. The polynomial used for the CRC computation is 0x1021. The CRC0 result may be initialized to one ...
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SFR Definition 16.1. CRC0CN: CRC0 Control Bit 7 6 Name R R Type 0 0 Reset SFR Page = All; SFR Address = 0x84 Bit Name 7:4 Unused Read = 0001b; Write = Don’t Care. 3 CRC0INIT CRC0 Result Initialization ...
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C8051F99x-C8051F98x SFR Definition 16.2. CRC0IN: CRC0 Data Input Bit 7 6 Name Type 0 0 Reset SFR Page = All; SFR Address = 0x85 Bit Name 7:0 CRC0IN[7:0] CRC0 Data Input. Each write to CRC0IN results in the written data ...
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SFR Definition 16.4. CRC0AUTO: CRC0 Automatic Control Bit 7 6 AUTOEN CRCDONE Name R/W R Type 0 1 Reset SFR Page = All; SFR Address = 0x9E Bit Name 7 AUTOEN Automatic CRC Calculation Enable. When AUTOEN is set to ...
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C8051F99x-C8051F98x SFR Definition 16.5. CRC0CNT: CRC0 Automatic Flash Sector Count Bit 7 6 Name Type 0 0 Reset SFR Page = All; SFR Address = 0x9A Bit Name 7:5 Unused Read = 00b; Write = Don’t Care. 4:0 CRC0CNT[4:0] Automatic ...
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CRC0 Bit Reverse Feature CRC0 includes hardware to reverse the bit order of each bit in a byte as shown in Figure 16.2. Each byte of data written to CRC0FLIP is read back bit reversed. For example, if 0xC0 ...
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C8051F99x-C8051F98x 17. Voltage Regulator (VREG0) C8051F99x-C8051F98x devices include an internal voltage regulator (VREG0) to regulate the internal core supply to 1.8 V from a VDD supply of 1.8 to 3.6 V. Electrical characteristics for the on-chip regulator are specified in ...
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Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: CIP-51 halts program execution Special Function Registers (SFRs) are initialized to their ...
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C8051F99x-C8051F98x 18.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin voltage tracks V pull-up) until the device is released from reset. After VDD settles above VPOR, a delay occurs before the device ...
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The enable state of the V a reset source is only altered by power-on and power-fail resets. For example, if the V de-selected as a reset source and disabled by software, then ...
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C8051F99x-C8051F98x SFR Definition 18.1. VDM0CN: VDD Supply Monitor Control Bit 7 6 Name VDMEN VDDSTAT VDDOK R/W R Type 1 Varies Varies Reset SFR Page = 0x0; SFR Address = 0xFF Bit Name 7 VDMEN V Supply Monitor Enable. DD ...
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Writing the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it. The missing clock detector reset is automatically disabled when the device is in the low power suspend or sleep ...
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C8051F99x-C8051F98x 18.9. Software Reset Software may force a reset by writing the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 following a software forced reset. The state of the RST pin is unaffected by this reset. ...
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SFR Definition 18.2. RSTSRC: Reset Source Bit 7 6 Name RTC0RE FERROR C0RSEF R/W R Type Varies Varies Varies Reset SFR Page = 0x0; SFR Address = 0xEF. Bit Name Description 7 RTC0RE SmaRTClock Reset Enable and Flag 6 FERROR ...
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C8051F99x-C8051F98x 19. Clocking Sources C8051F99x-C8051F98x devices include a programmable precision internal oscillator, an external oscillator drive circuit, a low power internal oscillator, and a SmaRTClock real time clock oscillator. The precision internal oscillator can be enabled/disabled and calibrated using the ...
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Programmable Precision Internal Oscillator All C8051F99x-C8051F98x devices include a programmable precision internal oscillator that may be selected as the system clock. OSCICL is factory calibrated to obtain a 24.5 MHz frequency. See Section “4. Electrical Characteristics” on page 46 ...
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C8051F99x-C8051F98x MHz 15 pF Figure 19.2. 25 MHz External Crystal Example Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL ...
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External RC Mode network is used as the external oscillator, the circuit should be configured as shown in Figure 19.1, Option 2. The RC network should be added to XTAL2, and XTAL2 should be configured for ...
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C8051F99x-C8051F98x 19.3.3. External Capacitor Mode If a capacitor is used as the external oscillator, the circuit should be configured as shown in Figure 19.1, Option 3. The capacitor should be added to XTAL2, and XTAL2 should be configured for analog ...
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Special Function Registers for Selecting and Configuring the System Clock The clocking sources on C8051F99x-C8051F98x devices are enabled and configured using the OSCICN, OSCICL, OSCXCN and the SmaRTClock internal registers. See Section “20. SmaRTClock (Real Time Clock)” on page ...
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C8051F99x-C8051F98x SFR Definition 19.2. OSCICN: Internal Oscillator Control Bit 7 6 Name IOSCEN IFRDY R/W R Type 0 0 Varies Reset SFR Page = 0x0; SFR Address = 0xB2 Bit Name 7 IOSCEN Internal Oscillator Enable. 0: Internal oscillator disabled. ...
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SFR Definition 19.3. OSCICL: Internal Oscillator Calibration Bit 7 6 Name SSE R/W R Type 0 Varies Varies Reset SFR Page = 0x0; SFR Address = 0xB3 Bit Name 7 SSE Spread Spectrum Enable. 0: Spread Spectrum clock dithering disabled. ...
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C8051F99x-C8051F98x SFR Definition 19.4. OSCXCN: External Oscillator Control Bit 7 6 Name XCLKVLD XOSCMD[2: Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xB1 Bit Name 7 XCLKVLD External Oscillator Valid Flag. Provides External Oscillator status ...
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SmaRTClock (Real Time Clock) C8051F99x-C8051F98x devices include an ultra low power 32-bit SmaRTClock Peripheral (Real Time Clock) with alarm. The SmaRTClock has a dedicated 32 kHz oscillator that can be configured for use with or without a crystal. No ...
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C8051F99x-C8051F98x 20.1. SmaRTClock Interface The SmaRTClock Interface consists of three registers: RTC0KEY, RTC0ADR, and RTC0DAT. These inter- face registers are located on the CIP-51’s SFR map and provide access to the SmaRTClock internal regis- ters listed in Table 20.1. The ...
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Using RTC0ADR and RTC0DAT to Access SmaRTClock Internal Registers The SmaRTClock internal registers can be read and written using RTC0ADR and RTC0DAT. The RTC0ADR register selects the SmaRTClock internal register that will be targeted by subsequent reads or writes. ...
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C8051F99x-C8051F98x 20.1.5. RTC0ADR Autoincrement Feature For ease of reading and writing the 32-bit CAPTURE and ALARM values, RTC0ADR automatically incre- ments after each read or write to a CAPTUREn or ALARMn register. This speeds up the process of setting an ...
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SFR Definition 20.1. RTC0KEY: SmaRTClock Lock and Key Bit 7 6 Name Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xAE Bit Name 7:0 RTC0ST SmaRTClock Interface Status. Provides lock status when read. Read: 0x02: SmaRTClock Interface ...
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C8051F99x-C8051F98x SFR Definition 20.2. RTC0ADR: SmaRTClock Address Bit 7 6 Name BUSY AUTORD R/W R/W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xAC Bit Name 7 BUSY SmaRTClock Interface Busy Indicator. Indicates SmaRTClock interface status. Writing ...