C8051F715-GMR Silicon Labs, C8051F715-GMR Datasheet - Page 88
C8051F715-GMR
Manufacturer Part Number
C8051F715-GMR
Description
8-bit Microcontrollers - MCU 8kB Cap Sense
Manufacturer
Silicon Labs
Datasheet
1.C8051F709-GQR.pdf
(306 pages)
Specifications of C8051F715-GMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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C8051F70x/71x
SFR Definition 15.1. CS0CN: Capacitive Sense Control
SFR Address = 0x9A; SFR Page = 0
88
Name
Reset
2:1
Bit
Type
7
6
5
4
3
0
Bit
CS0CMPEN
CS0CMPF
CS0BUSY
CS0PME
CS0INT
CS0EN
Unused
CS0EN
Name
R/W
7
0
CS0PME
CS0 Enable.
0: CS0 disabled and in low-power mode.
1: CS0 enabled and ready to convert.
CS0 Pin Monitor Event.
Set if any converter re-try requests have occurred due to a pin monitor event. This
bit remains set until cleared by firmware.
CS0 Interrupt Flag.
0: CS0 has not completed a data conversion since the last time CS0INT was
cleared.
1: CS0 has completed a data conversion.
This bit is not automatically cleared by hardware.
CS0 Busy.
Read:
0: CS0 conversion is complete or a conversion is not currently in progress.
1: CS0 conversion is in progress.
Write:
0: No effect.
1: Initiates CS0 conversion if CS0CM[2:0] = 000b, 110b, or 111b.
CS0 Digital Comparator Enable Bit.
Enables the digital comparator, which compares accumulated CS0 conversion
output to the value stored in CS0THH:CS0THL.
0: CS0 digital comparator disabled.
1: CS0 digital comparator enabled.
Read = 00b; Write = Don’t care
CS0 Digital Comparator Interrupt Flag.
0: CS0 result is smaller than the value set by CS0THH and CS0THL since the last
time CS0CMPF was cleared.
1: CS0 result is greater than the value set by CS0THH and CS0THL since the last
time CS0CMPF was cleared.
R/W
6
0
CS0INT
R/W
5
0
CS0BUSY CS0CMPEN
R/W
Rev. 1.0
4
0
Description
R/W
3
0
R
2
0
R
1
0
CS0CMPF
R
0
0
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