GTLP16612MTDX Fairchild Semiconductor, GTLP16612MTDX Datasheet

GTLP16612MTDX

Manufacturer Part Number

GTLP16612MTDX

Description

IC UNIV BUS TXRX 18BIT 56TSSOP

Manufacturer

Fairchild Semiconductor

Series

74GTLPr

Datasheet

1.GTLP16612MTDX.pdf (9 pages)

Specifications of GTLP16612MTDX

Logic Type

Universal Bus Transceiver

Number Of Circuits

18-Bit

Current - Output High, Low

32mA, 32mA

Voltage - Supply

3.15 V ~ 3.45 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

56-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

H&T Electronics

Part Number:

GTLP16612MTDX

Quantity:

1 000

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GTLP16612MEA

GTLP16612MTD

GTLP16612

18-Bit TTL/GTLP Universal Bus Transceiver

General Description

The GTLP16612 is an 18-bit universal bus transceiver

which provides TTL to GTLP signal level translation. The

device is designed to provide a high speed interface

between cards operating at TTL logic levels and a back-

plane operating at GTLP logic levels. High speed back-

plane operation is a direct result of GTLP’s reduced output

swing ( 1V), reduced input threshold levels and output

edge rate control which minimizes signal settling times.

GTLP is a Fairchild Semiconductor derivative of the Gun-

ning Transceiver Logic (GTL) JEDEC standard JESD8-3.

Fairchild’s GTLP has internal edge-rate control and is Pro-

cess, Voltage, and Temperature (PVT) compensated. Its

function is similar to BTL or GTL but with different driver

output levels and receiver threshold. GTLP output low volt-

age is typically less than 0.5V, the output high is 1.5V and

the receiver threshold is 1.0V.

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Order Number

Package Number

MS56A

MTD56

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS012390

Features

Bidirectional interface between GTLP and TTL logic

levels

Designed with an edge rate control circuit to reduce

output noise on GTLP port

receiver threshold adjustability

Special

consistent performance over variations of process,

supply voltage and temperature

TTL compatible Driver and Control inputs

Designed using Fairchild advanced CMOS technology

Bushold data inputs on A port to eliminate the need for

external pull-up resistors for unused inputs

Power up/down and power off high impedance for live

insertion

5V tolerant inputs and outputs on LVTTL port

Open drain on GTLP to support wired-or connection

Flow-through pinout optimizes PCB layout

D-type flip-flop, latch and transparent data paths

A Port outputs source/sink

REF

Package Description

pin provides external supply reference voltage for

PVT

compensation

March 1995

Revised March 2001

32 mA/ 32 mA

circuitry

www.fairchildsemi.com

provide

Related parts for GTLP16612MTDX

GTLP16612MTDX Summary of contents

Page 1

... GTLP’s reduced output swing ( 1V), reduced input threshold levels and output edge rate control which minimizes signal settling times. GTLP is a Fairchild Semiconductor derivative of the Gun- ning Transceiver Logic (GTL) JEDEC standard JESD8-3. Fairchild’s GTLP has internal edge-rate control and is Pro- cess, Voltage, and Temperature (PVT) compensated ...

Page 2

Pin Descriptions Pin Description Names OEAB A-to-B Output Enable (Active LOW) OEBA B-to-A Output Enable (Active LOW) CEAB A-to-B Clock Enable (Active LOW) CEBA B-to-A Clock Enable (Active LOW) LEAB A-to-B Latch Enable (Transparent HIGH) LEBA B-to-A Latch Enable (Transparent ...

Page 3

Logic Diagram 3 www.fairchildsemi.com ...

Page 4

Absolute Maximum Ratings Supply Voltage ( CCQ DC Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 5) 0. Output Sink Current into A Port I ...

Page 5

DC Electrical Characteristics Symbol 3.45V, CCQ CCQ Ports V 5.25V, CCQ GND I CCQ 3.45V Ports ...

Page 6

AC Electrical Characteristics Over recommended range of supply voltage and operating free-air temperature for B Port and for A Port Symbol From (Input PLH t PHL t LEAB PLH ...

Page 7

Test Circuits and Timing Waveforms Test Circuit for A Outputs C includes probes and jig capacitance. L Voltage Waveforms Pulse Duration (Vm 1.5V for A Port and 1.0V for B Port) Voltage Waveforms Setup and Hold Times (Vm 1.5V for ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide www.fairchildsemi.com Package Number MS56A 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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