74HC4052PW-Q100 NXP Semiconductors, 74HC4052PW-Q100 Datasheet - Page 14
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74HC4052PW-Q100
Manufacturer Part Number
74HC4052PW-Q100
Description
Encoders, Decoders, Multiplexers & Demultiplexers 4-ChanMux/Demux 10V
Manufacturer
NXP Semiconductors
Datasheet
1.74HC4052PW-Q100.pdf
(26 pages)
Specifications of 74HC4052PW-Q100
Product
Multiplexers / Demultiplexers
Logic Family
74HC
Number Of Lines (input / Output)
4 / 4
Propagation Delay Time
90 ns
Supply Voltage - Max
10 V
Supply Voltage - Min
2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-16
Minimum Operating Temperature
- 40 C
Number Of Input Lines
4
Number Of Output Lines
4
Operating Temperature Range
- 40 C to + 125 C
Operating Voltage
2 V to 10 V
Power Dissipation
500 mW
Part # Aliases
74HC4052PW-Q100,11
NXP Semiconductors
Table 10.
GND = 0 V; t
V
V
[1]
[2]
[3]
[4]
[5]
74HC_HCT4052_Q100
Product data sheet
Symbol
T
t
t
t
pd
on
off
is
os
Fig 13. Input (V
amb
is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
All typical values are measured at T
t
t
t
C
P
f
f
N = number of inputs switching;
{(C
C
C
V
pd
on
off
i
o
D
CC
= 40 C to +125 C
PD
= input frequency in MHz;
L
sw
= output frequency in MHz;
is the same as t
is the same as t
is the same as t
= output load capacitance in pF;
= C
= switch capacitance in pF;
L
is used to determine the dynamic power dissipation (P
= supply voltage in V.
+ C
PD
Parameter
propagation delay V
turn-on time
turn-off time
Dynamic characteristics for 74HCT4052-Q100
r
sw
V
= t
) V
CC
f
= 6 ns; C
2
is
CC
f
) to output (V
PHL
PZH and
PHZ
2
i
f
N + {(C
and t
and t
o
} = sum of outputs;
L
t
= 50 pF; for test circuit see
PZL
PLH
PLZ
Conditions
E, Sn to V
E, Sn to V
.
.
.
L
is
V
V
V
V
V
V
+ C
os
to V
CC
CC
CC
CC
CC
CC
amb
) propagation delays
sw
= 4.5 V; V
= 4.5 V; V
= 4.5 V; V
= 4.5 V; V
= 4.5 V; V
= 4.5 V; V
os
) V
V
= 25 C.
os
; R
V
os
os
is
output
74HC4052-Q100; 74HCT4052-Q100
All information provided in this document is subject to legal disclaimers.
CC
; R
; R
input
L
= ; see
2
L
L
f
= 1 k; see
= 1 k; see
EE
EE
EE
EE
EE
EE
o
Rev. 2 — 22 November 2012
} where:
= 0 V
= 4.5 V
= 0 V
= 4.5 V
= 0 V
= 4.5 V
50 %
Figure
Figure 13
D
50 %
in W).
Figure 14
Figure 14
t
PLH
…continued
15.
Dual 4-channel analog multiplexer/demultiplexer
001aad555
t
PHL
[2]
[3]
[4]
Min
-
-
-
-
-
-
Typ
-
-
-
-
-
-
© NXP B.V. 2012. All rights reserved.
Max
18
12
105
72
75
57
Unit
ns
ns
ns
ns
ns
ns
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