74LVTH16835MTD Fairchild Semiconductor, 74LVTH16835MTD Datasheet
74LVTH16835MTD
Specifications of 74LVTH16835MTD
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74LVTH16835MTD Summary of contents
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... MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 74LVTH16835MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...
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Connection Diagram www.fairchildsemi.com Pin Descriptions Pin Names Description A –A Data Register Inputs –Y 3-STATE Outputs 1 18 CLK Clock Pulse Input OE Output Enable Input LE Latch Enable Input Function Table Inputs CLK ...
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Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current Supply Current ...
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DC Electrical Characteristics Symbol Parameter V Input Clamp Diode Voltage IK V Input HIGH Voltage IH V Input LOW Voltage IL V Output HIGH Voltage OH V Output LOW Voltage OL I Bushold Input Minimum Drive I(HOLD) I Bushold Input ...
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AC Electrical Characteristics Symbol Parameter f CLK to Y MAX t Propagation Delay PLH PHL t Propagation Delay PLH PHL t Propagation Delay PLH t CLK to Y PHL t Output Enable ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide www.fairchildsemi.com Package Number MS56A 6 ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...