74VCX16500MTDX Fairchild Semiconductor, 74VCX16500MTDX Datasheet

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74VCX16500MTDX

Manufacturer Part Number
74VCX16500MTDX
Description
TXRX 18BIT UNIV BUS LV 56TSSOP
Manufacturer
Fairchild Semiconductor
Series
74VCXr
Datasheet

Specifications of 74VCX16500MTDX

Logic Type
Universal Bus Transceiver
Number Of Circuits
18-Bit
Current - Output High, Low
24mA, 24mA
Voltage - Supply
1.4 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 2004 Fairchild Semiconductor Corporation
74VCX16500MTD
74VCX16500
Low Voltage 18-Bit Universal Bus Transceivers with
3.6V Tolerant Inputs and Outputs
General Description
The VCX16500 is an 18-bit universal bus transceiver which
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is
HIGH. When LEAB is LOW, the A data is latched if CLKAB
is held at a HIGH or LOW logic level. If LEAB is LOW, the A
bus data is stored in the latch/flip-flop on the HIGH-to-LOW
transition of CLKAB. When OEAB is HIGH, the outputs are
active. When OEAB is LOW, the outputs are in a high-
impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active HIGH and OEBA is active
LOW).
The VCX16500 is designed for low voltage (1.4V to 3.6V)
V
The 74VCX16500 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Ordering Code:
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
CC
applications with I/O capability up to 3.6V.
Package Number
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS500089
Features
Note 1: To ensure the high-impedance state during power up or power
down, OEBA should be tied to V
should be tied to GND through a pull-down resistors; the minimum value of
the resistor is determined by the current-sourcing capability of the driver.
1.4V to 3.6V V
3.6V tolerant inputs and outputs
t
Power-down high impedance inputs and outputs
Supports live insertion/withdrawal (Note 1)
Static Drive (I
Uses patented noise/EMI reduction circuitry
Latchup performance exceeds 300 mA
ESD performance:
PD
2.9 ns max for 3.0V to 3.6V V
Human body model
Machine model 200V
24 mA @ 3.0V V
(A to B, B to A)
Package Description
OH
CC
/I
OL
supply operation
)
CC
CC
2000V
through a pull-up resistor and OEAB
March 1998
Revised October 2004
CC
www.fairchildsemi.com

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74VCX16500MTDX Summary of contents

Page 1

... Package Number 74VCX16500MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2004 Fairchild Semiconductor Corporation Features 1.4V to 3.6V V supply operation CC 3 ...

Page 2

Connection Diagram www.fairchildsemi.com Pin Descriptions Pin Names Description OEAB Output Enable Input for Direction (Active HIGH) OEBA Output Enable Input for Direction (Active LOW) LEAB, LEBA Latch Enable Inputs CLKAB, Clock Inputs CLKBA A ...

Page 3

Logic Diagram 3 www.fairchildsemi.com ...

Page 4

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATED Outputs Active (Note 6) 0 Input Diode Current ( Output ...

Page 5

DC Electrical Characteristics Symbol Parameter V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output Leakage OZ I Power Off Leakage Current OFF I Quiescent Supply Current CC I Increase in I per Input CC CC ...

Page 6

AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency C MAX C t Propagation Delay C PHL t Bus-to-Bus PLH C t Propagation Delay C PHL t Clock-to-Bus PLH C t Propagation Delay C PHL t LE-to-Bus PLH C t ...

Page 7

Dynamic Switching Characteristics Symbol Parameter V Quiet Output Dynamic OLP Peak Quiet Output Dynamic OLV Valley Quiet Output Dynamic OHV Valley V OH Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance I/O ...

Page 8

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-inverting Functions FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low ...

Page 9

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 8. Waveform for Inverting and Non-inverting Functions FIGURE 9. 3-STATE Output High Enable and Disable Times for Low ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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