GTLP10B320MTDX Fairchild Semiconductor, GTLP10B320MTDX Datasheet

GTLP10B320MTDX

Manufacturer Part Number

GTLP10B320MTDX

Description

IC UNIV BUS DVR 10BIT 56TSSOP

Manufacturer

Fairchild Semiconductor

Series

74GTLPr

Datasheet

1.GTLP10B320MTD.pdf (12 pages)

Specifications of GTLP10B320MTDX

Logic Type

Universal Bus Driver

Number Of Circuits

10-Bit

Current - Output High, Low

24mA, 24mA

Voltage - Supply

3.15 V ~ 3.45 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

56-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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GTLP10B320MTD

GTLP10B320

10-Bit LVTTL/GTLP Transceiver

with Split LVTTL Port and Feedback Path

General Description

The GTLP10B320 is a 10-bit Universal bus driver and

receiver, with separate LVTTL inputs and outputs and a

feedback path for diagnostics, that provides LVTTL to

GTLP signal level translation. High speed backplane oper-

ation is a direct result of GTLP’s reduced output swing

( 1V), reduced input threshold levels and output edge rate

control. The edge rate control minimizes bus settling time.

GTLP is a Fairchild Semiconductor derivative of the

Gunning Transistor logic (GTL) JEDEC standard JESD8-3.

Fairchild’s GTLP has internal edge-rate control and is pro-

cess, voltage and temperature (PVT) compensated. Its

function is similar to BTL and GTL but with different output

levels and receiver threshold. GTLP output low level is typ-

ically less than 0.5V, the output level high is 1.5V and the

receiver threshold is 1.0V.

Ordering Code:

Device is also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number

Package Number

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS500483

Features

Bidirectional interface between GTLP and LVTTL logic

levels

Variable edge rate control pin to select desired edge rate

on GTLP port (V

receiver threshold adjustibility

Split LVTTL inputs and outputs

Special PVT compensation circuitry to provide consis-

tent performance over variations of process, supply volt-

age and temperature

A feedback path for control and diagnostics monitoring

TTL compatible driver and control inputs

Designed using Fairchild advanced BiCMOS technology

Bushold data inputs on A port to eliminate the need for

external pull-up resistors for unused inputs

Power up/down and power off high impedance for live

insertion

Open drain on GTLP to support wired-or connection

Flow through pinout optimizes PCB layout

A Port source/sink 24mA/ 24mA

B Port sink 50mA

REF

Package Description

pin provides external supply reference voltage for

ERC

)

May 2001

Revised May 2001

www.fairchildsemi.com

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GTLP10B320MTDX Summary of contents

Page 1

... GTLP’s reduced output swing ( 1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3. Fairchild’s GTLP has internal edge-rate control and is pro- cess, voltage and temperature (PVT) compensated ...

Page 2

Pin Descriptions Pin Names Description OEB, OEC B Port, C Port Output Enable respectively (Active LOW GND, V Device Supplies CC REF LECLKAB, A-to-B, B-to-C Latch CLK respectively LECLKBC (Transparent Active HIGH) SEL Selects Internal Feedback Path SAB, ...

Page 3

Functional Tables I/O Path: SEL 1 (External Feedback Path) (Note 2) OEB OEC SAB SBC LECLKAB LECLKBC ...

Page 4

Logic Diagram www.fairchildsemi.com 4 ...

Page 5

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 6) DC Output Sink Current into C Port Output Source Current from ...

Page 6

DC Electrical Characteristics Symbol Test Conditions Ports V 3.45V Port GND Port and V 3.45V (Note 9) Control ...

Page 7

AC Electrical Characteristics Over recommended range of supply voltage and operating free air temperature GND for B Port and C ERC L From Symbol (Input PLH n t PHL t LECLKAB PLH t ...

Page 8

AC Electrical Characteristics Over recommended range of supply voltage and operating free air temperature GND for B Port and C ERC L From Symbol (Input PLH n t PHL t LECLKAB PLH t ...

Page 9

AC Electrical Characteristics Over recommended range of supply voltage and operating free air temperature for B Port and C ERC From Symbol (Input PLH n t PHL t ...

Page 10

AC Extended Electrical Characteristics Over recommended ranges of supply voltage and operating free air temperature for B Port and for C Port Symbol t (Note 14) OSLH t (Note 14) OSHL ...

Page 11

Test Circuits and Timing Waveforms Test Circuit for A Outputs Test Open PLH PHL PLZ PZL t /t GND PHZ PZH Note A: C includes probes and Jig capacitance. L Voltage Waveform - Propagation ...

Page 12

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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