DS26528GA4 Maxim Integrated, DS26528GA4 Datasheet
DS26528GA4
Specifications of DS26528GA4
Related parts for DS26528GA4
DS26528GA4 Summary of contents
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GENERAL DESCRIPTION The DS26528 is a single-chip 8-port framer and line interface unit (LIU) combination for T1, E1, and J1 applications. Each channel configurable, supporting both long-haul and short-haul lines. APPLICATIONS Routers Channel Service Units (CSUs) Data Service Units ...
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DETAILED DESCRIPTION.................................................................................................9 1 AJOR PERATING ODES 2. FEATURE HIGHLIGHTS ..................................................................................................10 2.1 G ......................................................................................................................................10 ENERAL 2 ............................................................................................................................10 INE NTERFACE 2 ....................................................................................................................10 LOCK YNTHESIZER 2 .....................................................................................................................10 ITTER TTENUATOR 2 ....................................................................................................................10 ...
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Receive Per-Channel Idle Code Insertion............................................................................................ 64 8.9.13 Per-Channel Loopback ........................................................................................................................ 64 8.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only) ................................................................... 64 8.9.15 T1 Programmable In-Band Loop Code Generator............................................................................... 65 8.9.16 T1 Programmable In-Band Loop Code Detection................................................................................ 66 8.9.17 ...
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Shift-DR.............................................................................................................................................. 264 13.1.6 Exit1-DR............................................................................................................................................. 264 13.1.7 Pause-DR........................................................................................................................................... 264 13.1.8 Exit2-DR............................................................................................................................................. 264 13.1.9 Update-DR ......................................................................................................................................... 264 13.1.10 Select-IR-Scan ............................................................................................................................... 264 13.1.11 Capture-IR ...................................................................................................................................... 265 13.1.12 Shift-IR............................................................................................................................................ 265 13.1.13 Exit1-IR........................................................................................................................................... 265 13.1.14 Pause-IR......................................................................................................................................... 265 13.1.15 Exit2-IR........................................................................................................................................... 265 13.1.16 Update-IR ....................................................................................................................................... 265 ...
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Figure 6-1. Block Diagram ......................................................................................................................................... 17 Figure 6-2. Detailed Block Diagram........................................................................................................................... 18 Figure 8-1. Backplane Clock Generation................................................................................................................... 28 Figure 8-2. Device Interrupt Information Flow Diagram............................................................................................. 31 Figure 8-3. IBO Multiplexer Equivalent Circuit—4.096MHz ...................................................................................... 36 Figure 8-4. IBO Multiplexer Equivalent Circuit—8.192MHz ...
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Figure 12-4. Motorola Bus Write Timing (BTS = 1) ................................................................................................. 254 Figure 12-5. Receive Framer Timing—Backplane (T1 Mode)................................................................................. 256 Figure 12-6. Receive-Side Timing, Elastic Store Enabled (T1 Mode)..................................................................... 257 Figure 12-7. Receive Framer Timing—Line Side .................................................................................................... 257 Figure 12-8. Transmit ...
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Table 4-1. T1-Related Telecommunications Specifications ...................................................................................... 14 Table 4-2. E1-Related Telecommunications Specifications ...................................................................................... 15 Table 5-1. Time Slot Numbering Schemes................................................................................................................ 16 Table 7-1. Detailed Pin Descriptions ......................................................................................................................... 19 Table 8-1. Reset Functions........................................................................................................................................ 29 Table 8-2. Registers Related to the Elastic ...
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Table 9-5. BERT Register List ................................................................................................................................... 98 Table 9-6. Global Register Bit Map............................................................................................................................ 99 Table 9-7. Framer Register Bit Map ........................................................................................................................ 100 Table 9-8. LIU Register Bit Map .............................................................................................................................. 108 Table 9-9. BERT Register Bit Map .......................................................................................................................... 108 Table 9-10. ...
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DETAILED DESCRIPTION The DS26528 is an 8-port monolithic device featuring independent transceivers that can be software configured for T1, E1 operation. Each transceiver is composed of a line interface unit, framer, HDLC controller, elastic store, and a ...
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FEATURE HIGHLIGHTS 2.1 General Member of the TEX-series transceiver family of devices. Software compatible with the DS26521 single, DS26522 dual, and DS26524 quad transceivers 256-pin TE-CSBGA package (17mm x 17mm, 1.00mm pitch) 3.3V supply with 5V tolerant inputs and ...
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Detailed alarm and status reporting with optional interrupt support Large path and line error counters − T1: BPV, CV, CRC-6, and framing bit errors − E1: BPV, CV, CRC-4, E-bit, and frame alignment errors − Timed or manual update modes ...
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HDLC Controllers One HDLC controller engine for each T1/E1 port Independent 64-byte Rx and Tx buffers with interrupt support Access FDL, Sa, or single DS0 channel Compatible with polled or interrupt driven environments 2.8 Test and Diagnostics IEEE 1149.1 ...
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APPLICATIONS The DS26528 is useful in applications such as: Routers Channel Service Units (CSUs) Data Service Units (DSUs) Muxes Switches Channel Banks T1/E1 Test Equipment DS26528 Octal T1/E1/J1 Transceiver 13 of 276 ...
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SPECIFICATIONS COMPLIANCE The DS26528 LIU meets all the latest relevant telecommunications specifications. the T1 and E1 specifications and relevant sections that are applicable to the DS26528. Table 4-1. T1-Related Telecommunications Specifications ANSI T1.102: Digital Hierarchy Electrical Interface AMI Coding ...
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Table 4-2. E1-Related Telecommunications Specifications ITU-T G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces Defines the 2048kbps bit rate—2048 ±50ppm; the transmission media are 75Ω coax or 120Ω twisted pair; peak-to- peak space voltage is ±0.237V; nominal pulse width is ...
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ACRONYMS AND GLOSSARY This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each 125μs T1 frame, there are 24 8-bit channels plus a framing bit assumed that the framing bit is ...
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BLOCK DIAGRAMS Figure 6-1. Block Diagram DS26528 LIU #7 LIU #6 LIU #5 LIU #4 LIU #3 LIU #2 RTIP RRING LINE INTERFACE TTIP UNIT TRING x8 MICRO PROCESSOR INTERFACE CONTROLLER PORT LIU #8 FRAMER #8 FRAMER #7 FRAMER ...
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Figure 6-2. Detailed Block Diagram TRANSCEIVER # TRANSMIT TTIPn LIU WAVEFORM SHAPER/LINE TRINGn DRIVER RECEIVE RTIPn LIU CLOCK/DATA RRINGn RECOVERY DS26528 DS26528 MICROPROCESSOR INTERFACE Tx BERT Tx FRAMER: B8ZS/ HDB3 ELASTIC ENCODE STORE Rx FRAMER: B8ZS/ HDB3 ELASTIC ...
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PIN DESCRIPTIONS 7.1 Pin Functional Description Table 7-1. Detailed Pin Descriptions NAME PIN TYPE TTIP1 A1, A2 TTIP2 H1, H2 TTIP3 J1 J2 Analog TTIP4 T1, T2 Output, High TTIP5 T15, T16 Impedance TTIP6 J15, J16 TTIP7 H15, H16 ...
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NAME PIN TYPE TSER1 F6 TSER2 E7 TSER3 R4 TSER4 N7 I TSER5 M10 TSER6 L11 TSER7 F10 TSER8 D12 TCLK1 C5 TCLK2 D7 TCLK3 P5 TCLK4 L8 I TCLK5 L10 TCLK6 N11 TCLK7 E10 TCLK8 B13 TSYSCLK P13 I ...
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NAME PIN TYPE TCHBLK/ A5 CLK1 TCHBLK/ C7 CLK2 TCHBLK/ L7 CLK3 TCHBLK/ P7 CLK4 O TCHBLK/ P9 CLK5 TCHBLK/ P11 CLK6 TCHBLK/ D10 CLK7 TCHBLK/ E11 CLK8 RSER1 E5 RSER2 D6 RSER3 N4 RSER4 N6 O RSER5 M11 RSER6 ...
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NAME PIN TYPE RMSYNC1/ C4 RFSYNC1 RMSYNC2/ C6 RFSYNC2 RMSYNC3/ P4 RFSYNC3 RMSYNC4/ P6 RFSYNC4 O RMSYNC5/ P10 RFSYNC5 RMSYNC6/ N12 RFSYNC6 RMSYNC7/ D11 RFSYNC7 RMSYNC8/ E12 RFSYNC8 RSIG1 D4 RSIG2 E6 RSIG3 M5 RSIG4 R5 O RSIG5 R11 RSIG6 ...
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NAME PIN TYPE RLF/ D3 LTC1 RLF/ E3 LTC2 RLF/ M3 LTC3 RLF/ N3 LTC4 O RLF/ N14 LTC5 RLF/ M14 LTC6 RLF/ E14 LTC7 RLF/ D14 LTC8 RCHBLK/ E4 CLK1 RCHBLK/ B5 CLK2 RCHBLK/ L6 CLK3 RCHBLK/ T5 CLK4 ...
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NAME PIN TYPE A12 C8 A11 A8 A10 B10 A1 A10 A0 C10 ...
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NAME PIN TYPE MCLK B7 I RESETB J12 I REFCLKIO A7 I/O DIGIOEN D8 I, Pullup JTRST L5 I, Pullup JTMS K4 I, Pullup JTCLK F5 I JTDI H4 I, Pullup O, High JTDO J4 impedance FUNCTION SYSTEM INTERFACE Master ...
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NAME PIN TYPE ATVDD1 B1 ATVDD2 G1 ATVDD3 K1 ATVDD4 R1 — ATVDD5 R16 ATVDD6 K16 ATVDD7 G16 ATVDD8 B16 ATVSS1 B2 ATVSS2 G2 ATVSS3 K2 ATVSS4 R2 — ATVSS5 R15 ATVSS6 K15 ATVSS7 G15 ATVSS8 B15 ARVDD1 D1 ARVDD2 ...
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FUNCTIONAL DESCRIPTION 8.1 Processor Interface Microprocessor control of the DS26528 is accomplished through the 28 hardware pins of the microprocessor port. The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the bus ...
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Figure 8-1. Backplane Clock Generation Pre MCLK Scaler PLL The reference clock for the backplane clock generator can be as follows: • External Master Clock. A prescaler can be used to generate frequency. • External Reference Clock ...
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Resets and Power-Down Modes A hardware reset is issued by forcing the RESETB pin to logic-low. The RESETB input pin resets all framers, LIUs, and BERTs. Note that not all registers are cleared to 00h on a reset condition. ...
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Initialization and Configuration 8.4.1 Example Device Initialization Sequence STEP 1: Reset the device by pulling the RESETB pin low, applying power to the device using the software reset bits outlined in Section 8.3. Clear all reset bits. ...
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Figure 8-2. Device Interrupt Information Flow Diagram Receive Remote Alarm Indication Clear Receive Alarm Condition Clear Receive Loss of Signal Clear Receive Loss of Frame Clear Receive Remote Alarm Indication Receive Alarm Condition Receive Loss of Signal Receive Loss of ...
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System Backplane Interface The DS26528 provides a versatile backplane interface that can be configured to the following: • Transmit and receive two-frame elastic stores • Mapping of T1 channels into a 2.048MHz backplane • IBO mode for multiple framers ...
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Elastic Stores Initialization There are two elastic store initializations that can be used to improve performance in certain applications: elastic store reset and elastic store align. Both of these involve the manipulation of the elastic store’s read and write ...
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Receiving Mapped T1 Channels from a 2.048MHz Backplane Setting the TSCLKM bit (TIOCR.4) enables the transmit elastic store to operate with a 2.048MHz backplane (32 time slots/frame). In this mode the user can choose which of the backplane channels ...
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Mapping E1 Channels onto a 1.544MHz Backplane The user can use the RSCLKM bit (RIOCR.4) to enable the receive elastic store to operate with a 1.544MHz backplane (24 channels / frame + F-bit). In this mode the user can ...
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Figure 8-3. IBO Multiplexer Equivalent Circuit—4.096MHz Port # 1 Backplane Interface Port # 2 Backplane Interface Port # 3 Backplane Interface Port # 4 Backplane Interface Port # 5 Backplane Interface Port # 6 Backplane Interface Port # 7 Backplane ...
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Figure 8-4. IBO Multiplexer Equivalent Circuit—8.192MHz Port # 1 Backplane Interface Port # 2 Backplane Interface Port # 3 Backplane Interface Port # 4 Backplane Interface Port # 5 Backplane Interface Port # 6 Backplane Interface Port # 7 Backplane ...
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Figure 8-5. IBO Multiplexer Equivalent Circuit—16.384MHz Port # 1 Backplane Interface Port # 2 Backplane Interface Port # 3 Backplane Interface Port # 4 Backplane Interface Port # 5 Backplane Interface Port # 6 Backplane Interface Port # 7 Backplane ...
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Table 8-5. RSER Output Pin Definitions PIN NORMAL USE Receive Serial Data RSER1 for Port 1 Receive Serial Data RSER2 for Port 2 Receive Serial Data RSER3 for Port 3 Receive Serial Data RSER4 for Port 4 Receive Serial Data ...
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Table 8-7. TSER Input Pin Definitions PIN NORMAL USE Transmit Serial Data TSER1 for Port 1 Transmit Serial Data TSER2 for Port 2 Transmit Serial Data TSER3 for Port 3 Transmit Serial Data TSER4 for Port 4 Transmit Serial Data ...
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Table 8-9. RSYNC Input Pin Definitions PIN NORMAL USE Receive Frame Pulse RSYNC1 for Port 1 Receive Frame Pulse RSYNC2 for Port 2 Receive Frame Pulse RSYNC3 for Port 3 Receive Frame Pulse RSYNC4 for Port 4 Receive Frame Pulse ...
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H.100 (CT Bus) Compatibility The registers used for controlling the H.100 backplane are The H.100 (or CT bus synchronous, bit-serial, TDM transport bus operating at 8.192MHz. The H.100 standard also allows compatibility modes to operate at 2.048MHz, ...
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Figure 8-7. TSSYNCIO (Input Mode) Input in H.100 (CT Bus) Mode 1 TSSYNCIO 2 TSSYNCIO TSYSCLK TSER BIT 8 NOTE 1: TSSYNCIO IN NORMAL OPERATION. NOTE 2: TSSYNCIO WITH H.100EN = 1 and TSSYNCINV = 1. NOTE 3: t (BIT ...
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Framers The DS26528 framer cores are software selectable for T1, J1, or E1. The receive framer locates the frame and multiframe boundaries and monitors the data stream for alarms also used for extracting and inserting signaling data, ...
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Table 8-11. ESF Framing Mode FRAME FRAMING NUMBER Table 8-12. SLC-96 ...
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FRAME NUMBER ...
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E1 Framing The E1 framing consists of FAS, NFAS detection as shown in Table 8-13. E1 FAS/NFAS Framing CRC-4 FRAME TYPE FAS C1 1 NFAS 0 2 FAS C2 3 NFAS 0 4 FAS C3 5 ...
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Table 8-14 shows registers that are related to setting up the framing. Table 8-14. Registers Related to Setting Up the Framer REGISTER Transmit Master Mode Register (TMMR) Transmit Control Register 1 (TCR1) Transmit Control Register 2 (TCR2) Transmit Control Register ...
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T1 Transmit Synchronizer The DS26528 transmitter can identify the D4 or ESF frame boundary, as well as the CRC multiframe boundaries within the incoming NRZ data stream at TSER. The TFM (TCR3.2) control bit determines whether the transmit synchronizer ...
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Signaling The DS26528 supports both software- and hardware-based signaling. Interrupts can be generated on changes of signaling data. The DS26528 is also equipped with receive-signaling freeze on loss of synchronization (OOF), carrier loss, or change of frame alignment. The ...
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Transmit-Signaling Operation There are two methods to provide transmit-signaling data. These are processor based (i.e., software based) or hardware based. Processor based refers to access through the transmit-signaling registers, TS1:TS16, while hardware based refers to using the TSIG pins. ...
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Receive-Signaling Operation There are two methods to access receive-signaling data and provide transmit-signaling data: processor based (i.e., software based) or hardware based. Processor based refers to access through the transmit- and receive-signaling registers, RS1:RS16. Hardware based refers to the ...
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Receive-Signaling Freeze The signaling data in the four multiframe signaling buffers is frozen in a known good state upon either a loss of synchronization (OOF event), carrier loss, or change of frame alignment mode, this action meets ...
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Receive SLC-96 Operation (T1 Mode Only SLC-96-based transmission scheme, the standard Fs-bit pattern is robbed to make room for a set of message fields. The SLC-96 multiframe is made up of six D4 superframes, thus it is ...
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Receive Bit-Oriented Code (BOC) Controller The DS26528 framers contain a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1, ESF mode in the data link bits. ...
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The Transmit FDL register (T1TFDL) contains the facility data link (FDL) information that inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first mode, only the lower six bits ...
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Additional E1 Receive Sa- and Si-Bit Receive Operation (E1 Mode) The DS26528, when operated in the E1 mode, provides for access to both the Sa and the Si bits via two methods. The first involves using the internal an ...
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Table 8-23 shows some of the registers related to maintenance and alarms. Table 8-23. Registers Related to Maintenance and Alarms REGISTER Receive Real-Time Status Register 1 (RRTS1) Receive Interrupt Mask Register 1(RIM1) Receive Latched Status Register 2 (RLS2) Receive Real-Time ...
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Status and Information Bit Operation When a particular event has occurred (or is occurring), the appropriate bit in one of these registers is set to 1. Status bits can operate in either a latched or real-time fashion. Some latched ...
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Table 8-24. T1 Alarm Criteria ALARM AIS (Blue Alarm) (See Note Bit 2 Mode (T1RCR2 12th F-Bit Mode (T1RCR2 (Note: This mode is RAI also referred to as the (Yellow “Japanese ...
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RAI- repetitive pattern within the ESF data link with a period of 1.08 seconds. It consists of sequentially interleaving 0.99 seconds of “00000000 11111111” (right-to-left ) with 90ms of “00111110 11111111.” The RRAI-CI bit is set when a ...
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Table 8-26. E1 Line Code Violation Counting Options E1 CODE VIOLATION SELECT (ERCNT. 8.9.9.2 Path Code Violation Count Register (PCVCR operation, the Path Code Violation Count register (PCVCR) records either Ft, Fs, or CRC-6 errors. When ...
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E-Bit Counter (EBCR) This counter is only available in E1 mode. E-Bit Count Register 1 (E1EBCR1) is the most significant word and E-Bit Count Register 2 (E1EBCR2) is the least significant word of a 16-bit counter that records far-end ...
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Transmit Per-Channel Idle Code Insertion Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. The Transmit Idle Code Definition registers (TIDR1:TIDR32) are provided to set the 8-bit idle code ...
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T1 Programmable In-Band Loop Code Generator The DS26528 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. Table 8-30. Registers Related to ...
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T1 Programmable In-Band Loop Code Detection The DS26528 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. Table 8-31. Registers Related to ...
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Framer Payload Loopbacks The framer, payload, and remote loopbacks are controlled by Receive Control Register 3 (RCR3). Table 8-32. Registers Related to Framer Payload Loopbacks RECEIVE CONTROL FRAMER REGISTER 3 (RCR3) ADDRESSES Framer Loopback Payload Loopback Remote Loopback Note: ...
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HDLC Controllers 8.10.1 Receive HDLC Controller The DS26528 has an enhanced HDLC controller that can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). The HDLC controller has a ...
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HDLC FIFO Control Control of the transmit and receive FIFOs is accomplished via the Receive HDLC FIFO Control (RHFC) and Transmit HDLC FIFO Control (THFC) registers. The FIFO control registers set the watermarks for the FIFO. When the receive ...
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Figure 8-9. Receive HDLC Example Start New Start New Message Buffer Message Buffer Configure Receive HDLC Controller (RHC, RHBSE, RHFC) Reset Receive HDLC Controller (RHC.6) Start New Start New Message Buffer Message Buffer Enable Interrupts RPE and RHWM NO Interrupt? ...
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Transmit HDLC Controller 8.10.2.1 FIFO Information The Transmit HDLC FIFO Buffer Available register (TFBA) indicates the number of bytes that can be written into the transmit FIFO. The count from this register informs the host as to how many ...
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Figure 8-10. HDLC Message Transmit Example Loop Action Required Work Another Process Configure Transmit HDLC Controller (THC1,THC2,THBSE,THFC) Reset Transmit HDLC Controller (THC.5) Enable TLWM Interrupt and Verify TLWM Clear Read TFBA N = TFBA[6..0] Push Message Byte ...
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Line Interface Units (LIUs) The DS26528 has eight identical LIU transmit and receive front-ends for the eight framers. Each LIU contains three sections: the transmitter, which waveshapes and drives the network line; the receiver, which handles clock and data ...
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Figure 8-11. Basic Balanced Network Connections F1 TX TIP RING TIP RING F4 NAME 1.25A Slow Blow Fuse 1.25A Slow Blow Fuse S1, S2 25V (max) ...
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Table 8-34. Recommended Supply Decoupling SUPPLY PINS DECOUPLING CAPACITANCE DVDD/DVSS 0.01μF + 0.1μF + 1μF + 10μF DVDDIO/DVSSIO 0.01μF + 0.1μF + 1μF + 10μF ATVDD/ATVSS 0.1μF (x8) + 1μF (x4) + 10μF (x2) ARVDD/ARVSS 0.1μF (x8) + 1μF (x4) ...
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LIU Operation The analog AMI/HDB3 waveforms off of the E1 lines or the AMI/B8ZS waveform off of the T1 lines are transformer coupled into the RTIP and RRING pins of the DS26528. The user has the option to use ...
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Transmitter NRZ data arrives from the framer transmitter; the data is encoded with HDB3 or B8ZS or AMI. The encoded data passes through a jitter attenuator enabled for the transmit path. A digital sequencer and DAC ...
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Transmit-Line Pulse Shapes The DS26528 transmitters can be selected individually to meet the pulse templates for E1 and T1/J1 modes. The T1/J1 pulse template is shown in shape can be configured for each LIU on an individual basis. The ...
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Figure 8-13. E1 Transmit Pulse Templates 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 8.11.2.2 Transmit Power-Down The individual transmitters can be powered down by setting the TPDE bit in the LIU ...
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Receiver The DS26528 contains eight identical receivers. All the receivers are designed to be fully software-selectable for E1, T1, and J1 without the need to change any external resistors. The device couples to the receive twisted ...
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Figure 8-14. Typical Monitor Application T1/E1 LINE Rm 8.11.3.4 Loss of Signal (LOS) The DS26528 uses both the digital and analog loss-detection method in compliance with the latest ANSI T1.231 for T1/J1 and ITU-T G.775, or ETS 300 233 for ...
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ANSI T1.231 for T1 and J1 Modes For short-haul mode, loss is declared if the received signal level is 3dB lower from the programmed value (based on Table 9-19) for a duration of 192-bit periods. Hence, if the sensitivity ...
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Jitter Attenuator The DS26528 contains a jitter attenuator for each LIU that can be set to a depth 128 bits via the JADS (LTRCR.4) bit in the LIU Transmit Receive Control register (LTRCR). The 128-bit mode ...
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LIU Loopbacks The DS26528 provides four LIU loopbacks for diagnostic purposes: analog loopback, local loopback, remote loopback, and dual loopback. In the loopback diagrams that follow, TSER, TCLK, RSER, and RCLK are inputs/outputs from the framer. Note that the ...
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Remote Loopback The outputs decoded from the receive LIU are looped back to the transmit LIU. The inputs from the transmit framer are ignored during a remote loopback. This loopback is conceptually shown in Figure 8-18. Remote Loopback TCLK ...
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Bit-Error-Rate Test (BERT) Function The bit-error-rate tester (BERT) block can generate and detect both pseudorandom and repeating bit patterns used to test and stress data-communication links. BERT functionality is dedicated for each of the transceivers. Table 8-40 ...
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The BERT block can generate and detect the following patterns: • The pseudorandom patterns 2E7-1, 2E9-1, 2E11-1, 2E15-1, and QRSS • A repetitive pattern from bits in length • Alternating (16-bit) words that flip every 1 to ...
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DEVICE REGISTERS Thirteen address bits are used to control the settings of the registers. The address map is compatible with the Dallas Semiconductor octal framer product, DS26401, as well as the DS26521, DS26522, and DS26524. The registers control functions ...
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Figure 9-1. Register Memory Map for the DS26528 Adrs = 0000 0000 0000 Adrs = 0000 1111 0000 Adrs = 0001 0000 0000 Adrs = 0001 1111 0000 Adrs = 0010 0000 0000 Adrs = 0100 0000 0000 Adrs = ...
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Global Register List Table 9-2. Global Register List ADDRESS NAME 0F0h GTCR1 0F1h GFCR 0F2h GTCR2 0F3h GTCCR 0F4h — 0F5h GLSRR 0F6h GFSRR 0F7h — 0F8h IDR 0F9h GFISR 0FAh GBISR 0FBh GLISR 0FCh GFIMR 0FDh GBIMR 0FEh ...
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Framer Register List Table 9-3. Framer Register List Note: Only the Framer 1 address is presented here.The same set of register definitions applies for Transceiver accordance with the DS26528 map offsets. Transceiver offset is (n ...
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ADDRESS NAME 03Fh RIDR32 040h RS1 041h RS2 042h RS3 043h RS4 044h RS5 045h RS6 046h RS7 047h RS8 048h RS9 049h RS10 04Ah RS11 04Bh RS12 04Ch RS13 04Dh RS14 04Eh RS15 04Fh RS16 050h LCVCR1 051h LCVCR2 ...
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ADDRESS NAME 083h RCR3 084h RIOCR 085h RESCR 086h ERCNT 087h RHFC 088h RIBOC 089h T1RSCC 08Ah RXPC 08B RBPBS 08Ch–08Fh — 090h RLS1 091h RLS2 092h RLS3 093 RLS4 094h RLS5 095h — RLS7 096h RLS7 097h — 098h ...
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ADDRESS NAME 0B7h–0BFh — 0C0h RBCS1 0C1h RBCS2 0C2h RBCS3 0C3h RBCS4 0C4h RCBR1 0C5h RCBR2 0C6h RCBR3 0C7h RCBR4 0C8h RSI1 0C9h RSI2 0CAh RSI3 0CBh RSI4 0CCh RGCCS1 0CDh RGCCS2 0CEh RGCCS3 0CFh RGCCS4 0D0h RCICE1 0D1h RCICE2 ...
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ADDRESS NAME 12Bh TIDR12 12Ch TIDR13 12Dh TIDR14 12Eh TIDR15 12Fh TIDR16 130h TIDR17 131h TIDR18 132h TIDR19 133h TIDR20 134h TIDR21 135h TIDR22 136h TIDR23 137h TIDR24 138h TIDR25 139h TIDR26 13Ah TIDR27 13Bh TIDR28 13Ch TIDR29 13Dh TIDR30 ...
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ADDRESS NAME 168h E1TRA 169h E1TSa4 16Ah E1TSa5 16Bh E1TSa6 16Ch E1TSa7 16Dh E1RSa8 16Eh–17Fh — 180h TMMR TCR1 181h TCR1 TCR2 182h TCR2 183h TCR3 184h TIOCR 185h TESCR 186h TCR4 187h THFC 188h TIBOC 189h TDS0SEL 18Ah TXPC ...
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ADDRESS NAME 1C9h THSCS2 1CAh THSCS3 1CBh THSCS4 1CCh TGCCS1 1CDh TGCCS2 1CEh TGCCS3 1CFh TGCCS4 1D0h PCL1 1D1h PCL2 1D2h PCL3 1D3h PCL4 1D4h TBPCS1 1D5h TBPCS2 1D6h TBPCS3 1D7h TBPCS4 1D8h–1FFh — FRAMER REGISTER LIST DESCRIPTION Transmit Hardware-Signaling ...
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LIU and BERT Register List Table 9-4. LIU Register List ADDRESS NAME 1000h LTRCR LIU Transmit Receive Control Register 1001h LTITSR LIU Transmit Impedance and Pulse Shape Selection Register 1002h LMCR LIU Maintenance Control Register 1003h LRSR LIU Real ...
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Register Bit Maps 9.2.1 Global Register Bit Map Table 9-6. Global Register Bit Map ADDR NAME BIT 7 0F0h GTCR1 — 0F1h GFCR IBOMS1 IBOMS0 0F2h GTCR2 — 0F3h GTCCR BPREFSEL3 BPREFSEL2 BPREFSEL1 BPREFSEL0 0F4h — — 0F5h GLSRR ...
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Framer Register Bit Map Table 9-7 contains the framer registers of the DS26528. Some registers have dual functionality based on the selection of T1/ operating mode in the shown below using two lines of text. The first ...
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ADDR NAME BIT 7 — 03Bh RIDR28 C7 T1RDMWE1 CH8 03Ch RIDR29 C7 T1RDMWE2 CH16 03Dh RIDR30 C7 T1RDMWE3 CH24 03Eh RIDR31 C7 — 03Fh RIDR32 C7 CH1-A 040h RS1 0 CH2-A 041h RS2 CH1-A CH3-A 042h RS3 CH2-A CH4-A ...
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ADDR NAME BIT 7 056h E1EBCR1 EB15 057h E1EBCR2 EB7 060h RDS0M B1 061h E1RFRID FR7 T1RFDL RFDL7 062h E1RRTS7 CSC5 063h T1RBOC — T1RSLC1 C8 064h E1RAF Si T1RSLC2 M2 065h E1RNAF Si T1RSLC3 S=1 066h E1RSiAF SiF14 067h ...
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ADDR NAME BIT 7 097h — — 098h RSS1 CH8 099h RSS2 CH16 09Ah RSS3 CH24 — 09Bh RSS4 CH32 C7 09Ch T1RSCD1 — C7 09Dh T1RSCD2 — 09Fh RIIR — 0A0h RIM1 RRAIC — 0A1h RIM2 — RIM3 (T1) ...
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ADDR NAME BIT 7 0C9h RSI2 CH16 0CAh RSI3 CH24 — 0CBh RSI4 CH32 0CCh RGCCS1 CH8 0CDh RGCCS2 CH16 0CEh RGCCS3 CH24 — 0CFh RGCCS4 CH32 0D0h RCICE1 CH8 0D1h RCICE2 CH16 0D2h RCICE3 CH24 — 0D3h RCICE4 CH32 ...
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ADDR NAME BIT 7 135h TIDR22 C7 136h TIDR23 C7 137h TIDR24 C7 — 138h TIDR25 C7 — 139h TIDR26 C7 — 13Ah TIDR27 C7 — 13Bh TIDR28 C7 — 13Ch TIDR29 C7 — 13Dh TIDR30 C7 — 13Eh TIDR31 ...
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ADDR NAME BIT 7 — 14Eh TS15 CH14-A — 14Fh TS16 CH15-A 150h TCICE1 CH8 151h TCICE2 CH16 152h TCICE3 CH24 — 153h TCICE4 CH32 161h TFRID FR7 TFDL7 162h T1TFDL — — 163h T1TBOC — T1TSLC1 C8 164h E1TAF ...
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ADDR NAME BIT 7 189h TDS0SEL — 18Ah TXPC — 18Bh TBPBS BPBSE8 — 18Eh TSYNCC — TESF 190h TLS1 TESF — 191h TLS2 — 192h TLS3 — 19Fh TIIR — TESF 1A0h TIM1 TESF — 1A1h TIM2 — 1A2h ...
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ADDR NAME BIT 7 CH32 1D4h TBPCS1 CH8 1D5h TBPCS2 CH16 1D6h TBPCS3 CH24 — 1D7h TBPCS4 CH32 * RLS6 is reserved for future use. ** Currently, RLS2 does not create an interrupt, therefore this bit is not used in ...
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Global Register Definitions Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status, framer interrupt status, IBO configuration, MCLK configuration, and BPCLK configuration. The global registers bit descriptions are presented in this section. ...
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Register Name GTCR1 Register Description: Global Transceiver Control Register 1 Register Address: 0F0h Bit # 7 6 Name — — Default 0 0 Bit 5: Receive Loss of Frame/Loss of Transmit Clock Indication Select (RLOFLTS RLOF/LTCx pin indicates ...
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Register Name: GFCR Description: Global Framer Control Register Register Address: 0F1h Bit # 7 6 Name IBOMS1 IBOMS0 Default 0 0 Bits 7 and 6: Interleave Bus Operation Mode Select 1 and 0 (IBOMS[1:0]). These bits determine the configuration of ...
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Register Name: GTCR2 Register Description: Global Transceiver Control Register 2 Register Address: 0F2h Bit # 7 6 Name — — Default 0 0 Bit 2: LOS Selection (LOSS). If this bit is set, the AL/RSIGF/FLOS pins can be driven with ...
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Register Name: GTCCR Register Description: Global Transceiver Clock Control Register Register Address: 0F3h Bit # 7 6 Name BPREFSEL3 BPREFSEL2 Default 0 0 Bits Backplane Clock Reference Selects (BPREFSEL[3:0]).These bits select which reference clock source will be ...
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Table 9-12. Master Clock Input Selection FREQSEL MPS1 MPS0 MCLK (MHz ±50ppm) 2.048 4.096 8.192 16.384 ...
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Register Name: GLSRR Register Description: Global LIU Software Reset Register Register Address: 0F5h Bit # 7 6 Name LSRST8 LSRST7 Default 0 0 Bit 7: Channel 8 LIU Software Reset (LSRST8). LIU logic and registers are reset with a 0-to-1 ...
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Register Name: GFSRR Register Description: Global Framer and BERT Software Reset Register Register Address: 0F6h Bit # 7 6 Name FSRST8 FSRST7 Default 0 0 Bit 7: Channel 8 Framer and BERT Software Reset (FSRST8). Framer logic and registers are ...
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Register Name: IDR Register Description: Device Identification Register Register Address: 0F8h Bit # 7 6 Name ID7 ID6 Default 0 1 Bits Device ID (ID[7:3]). The upper five bits of the IDR are used to display the ...
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Register Name: GFISR Register Description: Global Framer Interrupt Status Register Register Address: 0F9h Bit # 7 6 Name FIS8 FIS7 Default 0 0 The GFISR register reports the framer interrupt status for each of the eight T1/E1 framers. A logic ...
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Register Name: GBISR Register Description: Global BERT Interrupt Status Register Register Address: 0FAh Bit # 7 6 Name BIS8 BIS7 Default 0 0 The GBISR register reports the interrupt status for each of the eight T1/E1 bit error-rate testers (BERTs). ...
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Register Name: GLISR Register Description: Global LIU Interrupt Status Register Register Address: 0FBh Bit # 7 6 Name LIS8 LIS7 Default 0 0 The GLISR register reports the LIU interrupt status for each of the eight T1/E1 LIUs. A logic ...
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Register Name: GFIMR Register Description: Global Framer Interrupt Mask Register Register Address: 0FCh Bit # 7 6 Name FIM8 FIM7 Default 0 0 Bit 7: Framer 8 Interrupt Mask (FIM8 Interrupt masked Interrupt enabled. Bit 6: ...
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Register Name: GBIMR Register Description: Global BERT Interrupt Mask Register Register Address: 0FDh Bit # 7 6 Name BIM8 BIM7 Default 0 0 Bit 7: BERT Interrupt Mask 8 (BIM8 Interrupt masked Interrupt enabled. Bit 6: ...
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Register Name: GLIMR Register Description: Global LIU Interrupt Mask Register Register Address: 0FEh Bit # 7 6 Name LIM8 LIM7 Default 0 0 Bit 7: LIU Interrupt Mask 8 (LIM8 Interrupt masked Interrupt enabled. Bit 6: ...
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Framer Register Definitions See Table 9-3 for the complete framer register list. 9.4.1 Receive Register Definitions Register Name: RHC Register Description: Receive HDLC Control Register Register Address: 010h + (200h x n): where for ...
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Register Name: RHBSE Register Description: Receive HDLC Bit Suppress Register Register Address: 011h + (200h x n): where for Ports Bit # 7 6 Name BSE8 BSE7 Default 0 0 Bit 7: ...
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Register Name: RDS0SEL Register Description: Receive Channel Monitor Select Register Register Address: 012h + (200h x n): where for Ports Bit # 7 6 Name — — Default 0 0 Bits 4 ...
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Register Name: T1RCR2 (T1 Mode) Register Description: Receive Control Register 2 Register Address: 014h + (200h x n): where for Ports Bit # 7 6 Name — — Default 0 0 Bit ...
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Register Name: E1RSAIMR (E1 Mode Only) Register Description: Receive Sa-Bit Interrupt Mask Register Register Address: 014h + (200h x n): where for Ports Bit # 7 6 Name — — Default 0 ...
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Register Name: T1RBOCC (T1 Mode Only) Register Description: Receive BOC Control Register Register Address: 015h + (200h x n): where for Ports Bit # 7 6 Name RBR — Default 0 0 ...
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Register Name: T1RSAOI1, T1RSAOI2, T1RSAOI3 (T1 Mode Only) Register Description: Receive-Signaling All-Ones Insertion Registers Register Address: 038h, 039h, 03Ah + (200h x n): where for Ports Bit # (MSB) ...
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Register Name: RS1 to RS16 Register Description: Receive-Signaling Registers Register Address: 040h to 04Fh + (200h x n): where for Ports Mode: (MSB) CH1-A CH1-B CH1-C CH2-A CH2-B ...
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Register Name: LCVCR1 Register Description: Line Code Violation Count Register 1 Register Address: 050h + (200h x n): where for Ports Bit # 7 6 Name LCVC15 LCVC14 Default 0 0 Bits ...
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Register Name: FOSCR1 Register Description: Frames Out of Sync Count Register 1 Register Address: 054h + (200h x n): where for Ports Bit # 7 6 Name FOS15 FOS14 Default 0 0 ...
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Register Name: RDS0M Register Description: Receive DS0 Monitor Register Register Address: 060h + (200h x n): where for Ports Bit # 7 6 Name B1 B2 Default 0 0 Bits 7 to ...
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Register Name: T1RFDL (T1 Mode) Register Description: Receive FDL Register Register Address: 062h + (200h x n): where for Ports Bit # 7 6 Name RFDL7 RFDL6 Default 0 0 Note: This ...
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Register Name: T1RBOC (T1 Mode) Register Description: Receive BOC Register Register Address: 063h + (200h x n): where for Ports Bit # 7 6 Name — — Default 0 0 Bit 5: ...
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Register Name: T1RSLC1, T1RSLC2, T1RSLC3 (T1 Mode) Register Description: Receive SLC-96 Data Link Registers Register Address: 064h, 065h, 066h + (200h x n): where for Ports Bit # (MSB) ...
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Register Name: E1RNAF (E1 Mode) Register Description: E1 Receive Non-Align Frame Register Register Address: 065h + (200h x n): where for Ports Bit # 7 6 Name Si 1 Default 0 0 ...
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Register Name: E1RSiNAF (E1 Mode Only) Register Description: Receive Si Bits of the Non-Align Frame Register Register Address: 067h + (200h x n): where for Ports Bit # 7 6 Name SiF15 ...
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Register Name: E1RSa4 (E1 Mode Only) Register Description: Receive Sa4 Bits Register Register Address: 069h + (200h x n): where for Ports Bit # 7 6 Name RSa4F15 RSa4F13 Default 0 0 ...
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Register Name: E1RSa6 (E1 Mode Only) Register Description: Receive Sa6 Bits Register Register Address: 06Bh + (200h x n): where for Ports Bit # 7 6 Name RSa6F15 RSa6F13 Default 0 0 ...
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Register Name: E1RSa8 (E1 Mode Only) Register Description: Receive Sa8 Bits Register Register Address: 06Dh + (200h x n): where for Ports Bit # 7 6 Name RSa8F15 RSa8F13 Default 0 0 ...
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Register Name: Sa6CODE Register Description: Received Sa6 Codeword Register Register Address: 06Fh + (200h x n): where for Ports Bit # 7 6 Name — — Default 0 0 This register reports ...
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Register Name: RCR1 (T1 Mode) Register Description: Receive Control Register 1 Register Address: 081h + (200h x n): where for Ports Bit # 7 6 Name SYNCT RB8ZS Default 0 0 Note: ...
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Register Name: RCR1 (E1 Mode) Register Description: Receive Control Register 1 Register Address: 081h + (200h x n): where for Ports Bit # 7 6 Name — RHDB3 Default 0 0 Note: ...
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Register Name: T1RIBCC (T1 Mode) Register Description: Receive In-Band Code Control Register Register Address: 082h + (200h x n): where for Ports Bit # 7 6 Name — — Default 0 0 ...
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Register Name: E1RCR2 (E1 Mode) Register Description: Receive Control Register 2 Register Address: 082h + (200h x n): where for Ports Bit # 7 6 Name RSa8S RSa7S Default 0 0 Note: ...
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Register Name: RCR3 Register Description: Receive Control Register 3 Register Address: 083h + (200h x n): where for Ports Bit # 7 6 Name IDF — Default 0 0 Bit 7: Input ...
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Register Name: RIOCR Register Description: Receive I/O Configuration Register Register Address: 084h + (200h x n): where for Ports Bit # 7 6 Name RCLKINV RSYNCINV RCLKINV RSYNCINV Default 0 0 Bit ...
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Register Name: RESCR Register Description: Receive Elastic Store Control Register Register Address: 085h + (200h x n): where for Ports Bit # 7 6 Name RDATFMT RGCLKEN Default 0 0 Bit 7: ...
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Register Name: ERCNT Register Description: Error-Counter Configuration Register Register Address: 086h + (200h x n): where for Ports Bit # 7 6 Name 1SECS MCUS 1SECS MCUS Default 0 0 Bit 7: ...
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Register Name: RHFC Register Description: Receive HDLC FIFO Control Register Register Address: 087h + (200h x n): where for Ports Bit # 7 6 Name — — Default 0 0 Bits 1 ...
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Register Name: RIBOC Register Description: Receive Interleave Bus Operation Control Register Register Address: 088h + (200h x n): where for Ports Bit # 7 6 Name — IBS1 Default 0 0 Bits ...
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Register Name: T1RSCC (T1 Mode Only) Register Description: In-Band Receive Spare Control Register Register Address: 089h + (200h x n): where for Ports Bit # 7 6 Name — — Default 0 ...
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Register Name: RBPBS Register Description: Receive BERT Port Bit Suppress Register Register Address: 08Bh + (200h x n): where for Ports Bit # 7 6 Name BPBSE8 BPBSE7 Default 0 0 Bit ...
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Register Name: RLS1 Register Description: Receive Latched Status Register 1 Register Address: 090h + (200h x n): where for Ports Bit # 7 6 Name RRAIC RAISC Default 0 0 Note: All ...
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Register Name: RLS2 (T1 Mode) Register Description: Receive Latched Status Register 2 Register Address: 091h + (200h x n): where for Ports Bit # 7 6 Name RPDV — Default 0 0 ...
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Register Name: RLS2 (E1 Mode) Register Description: Receive Latched Status Register 2 Register Address: 091h + (200h x n): where for Ports Bit # 7 6 Name — CRCRC Default 0 0 ...
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Register Name: RLS3 (T1 Mode) Register Description: Receive Latched Status Register 3 Register Address: 092h + (200h x n): where for Ports Bit # 7 6 Name LORCC LSPC Default 0 0 ...
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Register Name: RLS3 (E1 Mode) Register Description: Receive Latched Status Register 3 Register Address: 092h + (200h x n): where for Ports Bit # 7 6 Name LORCC — Default 0 0 ...
Page 161
Register Name: RLS4 Register Description: Receive Latched Status Register 4 Register Address: 093h + (200h x n): where for Ports Bit # 7 6 Name RESF RESEM Default 0 0 Note: All ...
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Register Name: RLS5 Register Description: Receive Latched Status Register 5 (HDLC) Register Address: 094h + (200h x n): where for Ports Bit # 7 6 Name — — Default 0 0 Note: ...
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Register Name: RLS7 (T1 Mode) Register Description: Receive Latched Status Register 7 Register Address: 096h + (200h x n): where for Ports Bit # 7 6 Name — — Default 0 0 ...
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Register Name: RSS1, RSS2, RSS3, RSS4 Register Description: Receive-Signaling Status Registers Register Address: 098h, 099h, 09Ah, 09Bh + (200h x n): where for Ports Bit # (MSB ...
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Register Name: T1RSCD1 (T1 Mode Only) Register Description: Receive Spare Code Definition Register 1 Register Address: 09Ch + (200h x n): where for Ports Bit # 7 6 Name C7 C6 Default ...
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Register Name: RIIR Register Description: Receive Interrupt Information Register Register Address: 09Fh + (200h x n): where for Ports Bit # 7 6 Name — RLS7 Default RLS6 is ...
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Register Name: RIM2 (E1 Mode Only) Register Description: Receive Interrupt Mask Register 2 Register Address: 0A1h + (200h x n): where for Ports Bit # 7 6 Name — — Default 0 ...
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Register Name: RIM3 (T1 Mode) Register Description: Receive Interrupt Mask Register 3 Register Address: 0A2h + (200h x n): where for Ports Bit # 7 6 Name LORCC LSPC Default 0 0 ...
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Register Name: RIM3 (E1 Mode) Register Description: Receive Interrupt Mask Register 3 Register Address: 0A2h + (200h x n): where for Ports Bit # 7 6 Name LORCC — Default 0 0 ...
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Register Name: RIM4 Register Description: Receive Interrupt Mask Register 4 Register Address: 0A3h + (200h x n): where for Ports Bit # 7 6 Name RESF RESEM Default 0 0 Bit 7: ...
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Register Name: RIM5 Register Description: Receive Interrupt Mask Register 5 (HDLC) Register Address: 0A4h + (200h x n): where for Ports Bit # 7 6 Name — — Default 0 0 Bit ...
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Register Name: RIM7 (T1 Mode) Register Description: Receive Interrupt Mask Register 7 (BOC:FDL) Register Address: 0A6h + (200h x n): where for Ports Bit # 7 6 Name — — Default 0 ...
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Register Name: RSCSE1, RSCSE2, RSCSE3, RSCSE4 Register Description: Receive-Signaling Change of State Enable Registers Register Address: 0A8h, 0A9h, 0AAh, 0Abh + (200h x n): where for Ports Bit # ...
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Register Name: T1RUPCD1 (T1 Mode Only) Register Description: Receive Up Code Definition Register 1 Register Address: 0ACh + (200h x n): where for Ports Bit # 7 6 Name C7 C6 Default ...
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Register Name: T1RDNCD1 (T1 Mode Only) Register Description: Receive Down Code Definition Register 1 Register Address: 0AEh + (200h x n): where for Ports Bit # 7 6 Name C7 C6 Default ...
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Register Name: RRTS1 Register Description: Receive Real-Time Status Register 1 Register Address: 0B0h + (200h x n): where for Ports Bit # 7 6 Name — — Default 0 0 Note: All ...
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Register Name: RRTS3 (T1 Mode) Register Description: Receive Real-Time Status Register 3 Register Address: 0B2h + (200h x n): where for Ports Bit # 7 6 Name — — Default 0 0 ...
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Register Name: RRTS5 Register Description: Receive Real-Time Status Register 5 (HDLC) Register Address: 0B4h + (200h x n): where for Ports Bit # 7 6 Name — PS2 Default 0 0 Note: ...
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Register Name: RHF Register Description: Receive HDLC FIFO Register Register Address: 0B6h + (200h x n): where for Ports Bit # 7 6 Name RHD7 RHD6 Default 0 0 Bit 7: Receive ...
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Register Name: RCBR1, RCBR2, RCBR3, RCBR4 Register Description: Receive Channel Blocking Registers Register Address: 0C4h, 0C5h, 0C6h, 0C7h + (200h x n): where for Ports Bit # 7 6 ...
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Register Name: RGCCS1, RGCCS2, RGCCS3, RGCCS4 Register Description: Receive Gapped-Clock Channel Select Registers Register Address: 0CCh, 0CDh, 0CEh, 0CFh + (200h x n): where for Ports Bit # 7 ...
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Register Name: RBPCS1, RBPCS2, RBPCS3, RBPCS4 Register Description: Receive BERT Port Channel Select Registers Register Address: 0D4h, 0D5h, 0D6h, 0D7h + (200h x n): where for Ports Bit # ...
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Transmit Register Definitions Register Name: THC1 Register Description: Transmit HDLC Control Register 1 Register Address: 110h + (200h x n): where for Ports Bit # 7 6 Name NOFS TEOML Default ...
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Register Name: THBSE Register Description: Transmit HDLC Bit Suppress Register Register Address: 111h + (200h x n): where for Ports Bit # 7 6 Name TBSE8 TBSE7 Default 0 0 Bit 7: ...
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Register Name: E1TSACR (E1 Mode) Register Description: E1 Transmit Sa-Bit Control Register Register Address: 114h + (200h x n): where for Ports Bit # 7 6 Name SiAF SiNAF Default 0 0 ...
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Register Name: SSIE1, SSIE2, SSIE3, SSIE4 Register Description: Software-Signaling Insertion Enable Registers Register Address: 118h, 119h, 11Ah, 11Bh + (200h x n): where for Ports Bit # (MSB) 7 ...
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Register Name: TS1 to TS16 Register Description: Transmit-Signaling Registers Register Address: 140h to 14Fh + (200h x n): where for Ports Mode: Bit # (MSB Name ...
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Register Name: TCICE1, TCICE2, TCICE3, TCICE4 Register Description: Transmit Channel Idle Code Enable Registers Register Address: 150h, 151h, 152h, 153h + (200h x n): where for Ports Bit # ...
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Register Name: TFRID Register Description: Transmit Firmware Revision ID Register Register Address: 161h + (200h x n): where for Ports Bit # 7 6 Name FR7 FR6 Default 0 0 Bits 7 ...
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Register Name: T1TSLC1, T1TSLC2, T1TSLC3 (T1 Mode) Register Description: Transmit SLC-96 Data Link Registers Register Address: 164h, 165h, 166h + (200h x n): where for Ports Bit # (MSB) ...
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Register Name: E1TSiAF (E1 Mode) Register Description: Transmit Si Bits of the Align Frame Register Register Address: 166h + (200h x n): where for Ports Bit # 7 6 Name TSiF14 TSiF12 ...
Page 192
Register Name: E1TRA (E1 Mode Only) Register Description: Transmit Remote Alarm Register Register Address: 168h + (200h x n): where for Ports Bit # 7 6 Name TRAF15 TRAF13 Default 0 0 ...
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Register Name: E1TSa5 (E1 Mode Only) Register Description: Transmit Sa5 Bits Register Register Address: 16Ah + (200h x n): where for Ports Bit # 7 6 Name TSa5F15 TSa5F13 Default 0 0 ...
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Register Name: E1TSa7 (E1 Mode Only) Register Description: Transmit Sa7 Bits Register Register Address: 16Ch + (200h x n): where for Ports Bit # 7 6 Name TSa7F15 TSa7F13 Default 0 0 ...
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Register Name: TMMR Register Description: Transmit Master Mode Register Register Address: 180h + (200h x n): where for Ports Bit # 7 6 Name FRM_EN INIT_DONE Default 0 0 Bit 7: Framer ...
Page 196
Register Name: TCR1 (T1 Mode) Register Description: Transmit Control Register 1 Register Address: 181h + (200h x n): where for Ports Bit # 7 6 Name TJC TFPT Default 0 0 Note: ...
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Register Name: TCR1 (E1 Mode) Register Description: Transmit Control Register 1 Register Address: 181h + (200h x n): where for Ports Bit # 7 6 Name TTPT T16S Default 0 0 Note: ...
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Register Name: TCR2 (T1 Mode) Register Description: Transmit Control Register 2 Register Address: 182h + (200h x n): where for Ports Bit # 7 6 Name TFDLS TSLC96 Default 0 0 Note: ...
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Register Name: TCR2 (E1 Mode) Register Description: Transmit Control Register 2 Register Address: 182h + (200h x n): where for Ports Bit # 7 6 Name AEBE AAIS Default 0 0 Note: ...
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Register Name: TCR3 Register Description: Transmit Control Register 3 Register Address: 183h + (200h x n): where for Ports Bit # 7 6 Name ODF ODM ODF ODM Default 0 0 Bit ...