DS3172 Maxim Integrated, DS3172 Datasheet
DS3172
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DS3172 Summary of contents
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... GENERAL DESCRIPTION The DS3171, DS3172, DS3173, and DS3174 (DS317x) combine a DS3/E3 framer(s) and LIU(s) to interface to as many as four DS3/E3 physical copper lines. APPLICATIONS Access Concentrators Multiservice Access Platform (MSAP) SONET/SDH ADM and Muxes Multiservice Protocol Platform (MSPP) PBXs Digital Cross Connect ...
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... Frequencies (DS3, E3, STS-1) DETAILED DESCRIPTION The DS3171 (single), DS3172 (dual), DS3173 (triple), and DS3174 (quad) perform framing, formatting, and line transmission and reception. These devices contain integrated LIU(s), framer/formatter for M23 DS3, C-bit DS3, G.751 E3, G.832 E3 combination of the above signal formats. ...
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BLOCK DIAGRAMS Figure 1-1 shows the external components required at each LIU interface for proper operation. the functional block diagram of one channel DS3/E3 LIU. Figure 1-1. LIU External Connections for a DS3/E3 Port of a DS317x Device Transmit ...
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BLOCK DIAGRAMS 2 APPLICATIONS 3 FEATURE DETAILS 3 ........................................................................................................................................ 13 LOBAL EATURES 3.2 R DS3/E3 LIU F ECEIVE EATURES 3.3 R DS3/E3 F ECEIVE RAMER 3.4 T DS3/E3 F RANSMIT ORMATTER 3.5 T DS3/E3 LIU F RANSMIT ...
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Sources of Clock Output Pin Signals ................................................................................................... 54 10.2.3 Line IO Pin Timing Source Selection ................................................................................................... 57 10.2.4 Clock Structures On Signal IO Pins ..................................................................................................... 59 10.2.5 Gapped Clocks..................................................................................................................................... 60 10 ............................................................................................................................ 60 ESET AND OWER ...
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Transmit Line Interface ...................................................................................................................... 105 10.10.5 Receive Line Interface ....................................................................................................................... 105 10.10.6 B3ZS/HDB3 Decoder ......................................................................................................................... 105 10.11 BERT......................................................................................................................................................... 107 10.11.1 General Description ........................................................................................................................... 107 10.11.2 Features ............................................................................................................................................. 107 10.11.3 Configuration and Monitoring............................................................................................................. 107 10.11.4 Receive Pattern Detection ................................................................................................................. 108 ...
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JTAG ID C ......................................................................................................................................... 214 ODES 13.5 JTAG F T UNCTIONAL IMING 13 ...................................................................................................................................................... 214 INS 14 PIN ASSIGNMENTS 15 PACKAGE INFORMATION 15.1 400-L TE-PBGA (27 EAD 16 PACKAGE THERMAL INFORMATION 17 DC ELECTRICAL CHARACTERISTICS 18 AC ...
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Figure 1-1. LIU External Connections for a DS3/E3 Port of a DS317x Device ........................................................... 3 Figure 1-2. DS317x Functional Block Diagram ........................................................................................................... 3 Figure 2-1. Four-Port DS3/E3 Line Card ................................................................................................................... 12 Figure 6-1. DS3/E3 SCT Mode.................................................................................................................................. 19 Figure 6-2. DS3/E3 ...
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... Figure 13-3. JTAG Functional Timing...................................................................................................................... 214 Figure 14-1. DS3174 Pin Assignments—400-Lead PBGA ..................................................................................... 215 Figure 14-2. DS3173 Pin Assignments—400-Lead PBGA ..................................................................................... 216 Figure 14-3. DS3172 Pin Assignments—400-Lead PBGA ..................................................................................... 216 Figure 14-4. DS3171 Pin Assignments—400-Lead PBGA ..................................................................................... 217 Figure 18-1. Clock Period and Duty Cycle Definitions............................................................................................. 222 Figure 18-2 ...
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Table 4-1. Standards Compliance ............................................................................................................................. 16 Table 7-1. HDB3/B3ZS/AMI LIU Mode Configuration Registers ............................................................................... 21 Table 7-2. HDB3/B3ZS/AMI Non-LIU Mode Configuration Registers ....................................................................... 23 Table 7-3. UNI Line Interface Mode Configuration Registers.................................................................................... 24 Table 8-1. DS3174 Short Pin Descriptions................................................................................................................ 25 ...
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Table 12-13. Per Port Common Register Map ........................................................................................................ 134 Table 12-14. BERT Register Map............................................................................................................................ 144 Table 12-15. Transmit Side B3ZS/HDB3 Line Encoder/Decoder Register Map ..................................................... 152 Table 12-16. Receive Side B3ZS/HDB3 Line Encoder/Decoder Register Map ...................................................... 153 Table 12-17. Transmit ...
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APPLICATIONS • Access Concentrators • Multiservice Access Platforms • ATM and Frame Relay Equipment • Routers and Switches • SONET/SDH ADM • SONET/SDH Muxes • PBXs • Digital Cross Connect • PDH Multiplexer/Demultiplexer • Test Equipment • Integrated Access ...
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... FEATURE DETAILS The following sections describe the features provided by the DS3171 (single), DS3172 (dual), DS3173 (triple), and DS3174 (quad) single-chip transceivers (framers and LIUs, SCTs). 3.1 Global Features • Supports the following transmission protocols: • C-bit DS3 • M23 DS3 • G.751 E3 • ...
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FEAC port for DS3 FEAC channel can be configured to send one codeword, one codeword continuously, or two different codewords back-to-back to send DS3 Line Loopback commands • 16-byte Trail Trace Buffer port for the G.832 trail access point ...
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Trail Trace Buffer Features • Each port has a dedicated Trail Trace Buffer for E3-G.832 link management • Extraction and storage of the incoming G.832 trail access point identifier in a 16-byte receive register • Insertion of the outgoing ...
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STANDARDS COMPLIANCE Table 4-1. Standards Compliance SPECIFICATION ANSI T1.102-1993 Digital Hierarchy – Electrical Interfaces T1.107-1995 Digital Hierarchy – Formats Specification T1.231-1997 Digital Hierarchy – Layer 1 In-Service Digital Transmission Performance Monitoring T1.404-1994 Network-to-Customer Installation – DS3 Metallic Interface Specification ...
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ACRONYMS AND GLOSSARY Definition of the terms used in this Datasheet: • CCM – Clear Channel Mode • CLAD – Clock Rate Adapter • Clear Channel – A Datastream with no framing included, also known as Unframed • FRM ...
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MAJOR OPERATIONAL MODES The major operational modes are determined by the FM[2:0] framer mode bits and a few other control bits. Unused features are powered down and the data paths are held in reset. The configuration registers of the ...
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Figure 6-1. DS3/E3 SCT Mode TPOSn/TDATn TNEGn TLCLKn DS3/E3 TXPn Transmit LIU TXNn RDATn RNEGn/ RLCVn RLCLKn DS3/E3 RXPn Receive RXNn LIU Clock Rate Adapter TAIS TUA1 DS3 / E3 B3ZS/ Transmit HDB3 Formatter Encoder Trail FEAC Trace HDLC Buffer ...
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DS3/E3 Clear Channel Mode This mode bypasses the framer/formatter for unchannelized datastreams that don’t include DS3 framing or E3 framing. MODE FM[2:0] Clear Channel 1XX Figure 6-2. DS3/E3 Clear Channel Mode TPOSn/ TDATn TNEGn TLCLKn DS3/E3 TXPn Transmit LIU ...
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MAJOR LINE INTERFACE OPERATING MODES The line interface modes provide the following functions: 1. Enabling/disabling of RX and TX LIU. 2. Enabling/Disabling of jitter attenuator (JA). 3. Selection of the location of JA, i. path. 4. ...
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Figure 7-1. HDB3/B3ZS/AMI LIU Mode TXPn DS3/E3 Encoder Transmit TXNn LIU DS3/E3 RXPn Receive RXNn Decoder LIU Clock Rate Adapter TAIS TUA1 B3ZS/ HDB3 FROM FRAMING LOGIC OR EXTERNAL PINS B3ZS/ TO FRAMING LOGIC HDB3 OR EXTERNAL PINS 22 n ...
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HDB3/B3ZS/AMI Non-LIU Line Interface Mode The Non-LIU Line Interface Mode disables the LIU and a digital representation of AMI is output/input on the TPOSn/TNEGn signals and the RPOSn/RNEGn signals. Selection between AMI and HDB3/B3ZS is made via the LINE.TCR ...
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UNI Line Interface Mode This mode is valid for all framing modes, providing a digital NRZ input/output on RDATn and TDATn and clocked by RLCLKn and TLCLKn. The B3ZS/HDB3 decoder/encoder block is disabled except for the BPV counter, which ...
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PIN DESCRIPTIONS Note: In JTAG mode, all digital pins are bidirectional to increase the effectiveness of board level ATPG patterns for isolation of interconnect failures. 8.1 Short Pin Descriptions Table 8-1. DS3174 Short Pin Descriptions n=1,2,3,4 (port number); Ipu ...
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NAME TYPE D[15] IO D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[10] I A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] / BSWAP ALE ...
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NAME TYPE JTRST Ipu CLKA I CLKB IO CLKC IO VSS PWR VDD PWR AVDDRn PWR AVDDTn PWR AVDDJn PWR AVDDC PWR NC NC FUNCTION JTAG Reset (active low with pull-up) CLAD Clock A Clock B Clock C POWER Ground, ...
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Detailed Pin Descriptions Table 8-2. Detailed Pin Descriptions n=1,2,3,4 (port number); Ipu (input with pullup), Oz (output tri-stateable) (needs an external pullup or pulldown resistor to keep from floating), Oa (Analog output), Ia (analog input), IO (Bidirectional inout); all ...
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PIN NAME TYPE Receive Positive analog RXPn: This pin and the RXNn pin form a differential AMI input which is coupled to the outbound 75Ω coaxial cable through a 2:1 step-up transformer RXPn Ia RX LIU is enabled and is ...
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PIN NAME TYPE Transmit Overhead TOHn: When the port framer is configured for one of the DS3 or E3 framing modes, this signal will be used to over-write the DS3 or E3 framing overhead bits when TOHENn is active. In ...
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PIN NAME TYPE DS3/E3 SERIAL DATA OVERHEAD INTERFACE Transmit Line Clock Input TCLKIn: This clock is typically used for the reference clock for the TSOFIn, TSERn, and TSOFOn / TDENn signals but can also be used as the reference for ...
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PIN NAME TYPE Framer Start Of Frame / Data Enable See Table 10-21. TSOFOn: When the port framer is configured for the DS3 or E3 framed modes and the TSOFOn pin function is selected, this signal is used to indicate ...
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PIN NAME TYPE Bi-directional 16 or 8-bit data bus This bus is tri-state when RST pin is low or CS pin is high. D[15:0] IO D[15:0]: A 16-bit or 8-bit data bus used to input data during register writes, and ...
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PIN NAME TYPE General-Purpose IO 1 GPIO1 IO GPIO1: This signal is configured general-purpose IO pin alarm output signal for port 1. General-Purpose IO 2 GPIO2 IO GPIO2: This signal is configured ...
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PIN NAME TYPE Clock A CLKA: This clock input is a DS3 signal(44.736MHz +/-20ppm) when the CLAD is disabled or it CLKA I is one of the CLAD reference clock signals when the CLAD is enabled. Clock B CLKB: This ...
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Pin Functional Timing 8.3.1 Line IO 8.3.1.1 B3ZS/HDB3/AMI Mode Transmit Pin Functional Timing There is no suggested time alignment between the TXPn, TXNn and TX LINE signals and the TLCLKn clock signal. The TX DATA signal is not a ...
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Figure 8-2. TX Line IO HDB3 Functional Timing Diagram TLCLK (TX DATA) TPOS TNEG TXP BIAS V TXN (TX LINE) - 8.3.1.2 B3ZS/HDB3/AMI Mode Receive Pin Functional Timing There is no suggested time alignment between the RXPn, ...
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Figure 8-4. RX Line IO HDB3 Functional Timing Diagram RLCLK (RX DATA) RPOS RNEG RXP BIAS V RXN (RX LINE) - 8.3.1.3 UNI Mode Transmit Pin Functional Timing The TDATn pin is available when the line interface ...
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Figure 8-6. RX Line IO UNI Functional Timing Diagram RLCLK RDAT RLVC INC BPV COUNTER TWICE 8.3.2 DS3/E3 Framing Overhead Functional Timing Figure 8-7 shows the relationship between the DS3 receive overhead port pins. Figure 8-7. DS3 Framing Receive Overhead ...
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Figure 8-10 shows the relationship between the DS3 transmit overhead port pins. Figure 8-10. DS3 Framing Transmit Overhead Port Timing TOHCLK TOHSOF TOHEN TOH F73 C73 F74 X1 F11 Figure 8-11 shows the relationship between ...
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Figure 8-13. DS3 SCT Mode Transmit Serial Interface Pin Timing TCLKO or TCLKI TSOFO TSOFI DS3 TGCLK DS3 TSER DS3 TDEN Figure 8-14. E3 G.751 SCT Mode Transmit Serial Interface Pin Timing TCLKO or TCLKI TSOFO ...
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Figure 8-16. DS3 SCT Mode Receive Serial Interface Pin Timing RCLKO or RCLKI RSOFO DS3 RGCLK DS3 RSER X1 DS3 RDEN Figure 8-17. E3 G.751 SCT Mode Receive Serial Interface Pin Timing RCLKO or RCLKI RSOFO ...
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Figure 8-19. 16-Bit Mode Write A[0]/BSWAP 0x2B0 A[10:1] D[15:0] 0x1234 RDY Z Note: Address 0x2B0 = 0x1234 Figure 8-20. 16-Bit Mode Read A[0]/BSWAP 0x2B0 A[10:1] D[15:0] 0x1234 RDY Z Note: Address 0x2B0 = 0x1234 ...
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Figure 8-21. 8-Bit Mode Write A[0]/BSWAP A[10:1] 0x2B0 D[7:0] 0x34 RDY Z Note: Address 0x2B0 = 0x34 0x2B1 = 012 Figure 8-22. 8-Bit Mode Read A[0]/BSWAP 0x2B0 A[10:1] D[7:0] 0x34 RDY Z Note: Address ...
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Figure 8-23. 16-Bit Mode without Byte Swap A[0]/BSWAP 0x2B0 A[10:1] D[15:0] 0x1234 RDY Z Note: Address 0x2B0 = 0x1234 0x2B2 = 0x5678 Figure 8-24. 16-Bit Mode with Byte Swap A[0]/BSWAP 0x2B0 A[10:1] D[15:0] 0x3412 ...
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Figure 8-25. Clear Status Latched Register on Read A[0]/BSWAP 0x1C0 A[10:1] D[15:0] 0xFFFF RDY Z Figure 8-26. Clear Status Latched Register on Write A[0]/BSWAP 0x1C0 A[10:1] D[15:0] 0xFFFF RDY Figure 8-27 and Figure ...
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Figure 8-27. RDY Signal Functional Timing Write A[0]/BSWAP 0x2B0 A[10:1] D[15:0] 0x1234 RDY Z Figure 8-28. RDY Signal Functional Timing Read A[0]/BSWAP 0x1C0 A[10:1] D[15:0] 0xFFFF RDY Z See also Figure 18-7 and Figure ...
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... STEP 1: Check Device ID Code: Before any testing can be done, device ID code, which is stored in GL.IDR, should be checked against device ID codes shown below to ensure correct device is being used. Current device ID codes are: DS3171 rev 1.0: o DS3172 rev 1.0: o DS3173 rev 1.0: o DS3174 rev 1.0: o STEP 2: Initialize the Device. ...
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Table 9-1. Configuration of Port Register Settings Note: The Line Mode has been configured with the LIU enabled and the JA in the receive path (LM[2:0] = 011) for all modes. Only Port 1 registers have been displayed. Test the ...
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FUNCTIONAL DESCRIPTION 10.1 Processor Bus Interface 10.1.1 8/16 Bit Bus Widths The external processor bus can be sized for bits using the WIDTH pin. When in 8-bit mode (WIDTH=0), the address is composed of all the ...
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The clear on read mode is simpler since the bits that were read as being set will be cleared automatically. This method will work well in a software system where multiple tasks do not read the same latched status register. ...
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Figure 10-1. Interrupt Structure SRL bit SRIE bit SRL bit SRIE bit SRL bit SRIE bit BLOCK LATCHED STATUS and INTERRUPT ENABLE REGISTERS Figure 10-1 not only tells the user how to determine which event caused the interrupt, it also ...
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LIU Enabled, Loop Timing Enabled In this mode, the receive LIU sources the clock for both the receive and ...
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LIU Disabled - CLAD Timing Enabled – this mode, the RLCLKn pins source the clock for the receive logic and one of the CLAD clocks sources the clock for the transmit logic. 10.2.2 Sources of Clock ...
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Table 10-3. Source Selection of TLCLK Clock Signal Signal LOOPT LBM[2:0] PORT. (PORT.CR4) CR3 TLCLKn 1 XXX 1 XXX 0 010 0 110 0 010 0 110 0 011 0 011 0 000 0 001 0 100 0 10X 0 ...
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Table 10-4. Source Selection of TCLKOn (internal TX clock) Signal LOOPT LBM[2:0] PORT.CR3 TCLKOn Figure 10-3 shows the source of the RCLKOn signals. Figure 10-3. Internal RX Clock RLCLK Rx LIU CLOCK TCLKO Table ...
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Line IO Pin Timing Source Selection The line IO pins can use any input clock pin (RLCLKn or TCLKIn) or output clock pin (TLCLKn, RCLKOn, or TCLKOn) for its clock pin and meet the AC timing specifications as long ...
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Table 10-7. Transmit Framer Pin Signal Timing Source Select LBM[2:0] 1 XXX 1 XXX 1 XXX 0 PLB (011) or DLB (100) or ALB(001) 0 PLB (011) or DLB (100) 0 DLB&LLB (110) 0 LLB (010) 0 not LLB, DLB ...
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Table 10-9. Receive Framer Pin Signal Timing Source Select LBM[2:0] 1 XXX 1 XXX 1 XXX 0 PLB (011) or DLB (100) or ALB(001) 0 PLB (011) or DLB (100) 0 DLB&LLB (110) 0 LLB (010) 0 not LLB, DLB ...
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Figure 10-4. Example IO Pin Clock Muxing TSER PIN INVERT TCLKI PIN INVERT RLCLK PIN INVERT RX LIU CLK CLAD CLOCKS DS3 CLK E3 CLK STS-1 CLK 10.2.5 Gapped Clocks The transmit and receive output clocks can be gapped in ...
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The external RST pin and the global reset bit in the global configuration register (GL.CR1.RST) are combined to create an internal global reset signal. The global reset signal resets all the status and control registers on the chip, except the ...
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Table 10-10. Reset and Power-Down Sources Register bit states - F0: Forced to 0, F1: Forced Set Set Don’t care Forced: Internally controlled Set: User controlled PIN REGISTER BITS 0 F0 ...
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FEBE is enabled. Transmit clock comes from the CLAD CLKA pin. The pin inversion on all pins is disabled. Individual blocks are reset and powered down when not used determined by the settings in the line mode bits ...
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The CLAD MODE inputs to the clock rate adapter are composed of CLAD[3:0] control bits (located in the Register) which determines which pins are input and output and which clock rate is on which pin. When CLAD[3:0]=00XX, the PLL circuits ...
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Table 10-12. Global 8 kHz Reference Source Table GL.CR2. GL.CR2. Source G8KIS G8KRS[2:0] 0 000 None, the 8KHZ divider is disabled. 0 001 Derived from CLAD DS3 clock output or CLKA pin if CLAD is disabled. (Note: CLAD is disabled ...
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One Second Reference Generation The one-second-reference signal is used as an option to update the performance registers on a precise one- second interval. The generated internal signal should be about 50% duty cycle and it is derived from the ...
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Table 10-16. GPIO Port Alarm Monitor Select PORT.CR4 GPIO(A/B)[3:0] 0000 X 0001 X 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 X 1100 1101 X 1110 1111 X X 10.4.5 Performance Monitor Counter Update Details The performance monitor ...
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Figure 10-8. Performance Monitor Update Logic PORT.CR1.PMUM PORT.CR1.PMU GL.CR1.GPMU 00 GPIO8(GPMU) PIN 01 1X ONE SEC GL.CR1.GPM 10.4.6 Transmit Manual Error Insertion Transmit errors can be inserted in some of the functional blocks. These errors can be inserted using register ...
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Figure 10-9. Transmit Error Insert Logic PORT.CR.MEIMS PORT.CR.TMEI GL.CR1.MEIMS GL.CR1.TMEI GPIO6 PIN (TMEI) 10.5 Per Port Resources 10.5.1 Loopbacks There are several loop back paths available. The following table lists the loopback modes available for analog loopback (ALB), line loopback ...
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Figure 10-10 highlights where each loopback mode is located and gives an overall view of the various loopback paths available. Figure 10-10. Loopback Modes B3ZS/ DS3/E3 HDB3 Transmit Encoder LIU DS3/E3 B3ZS/ Receive HDB3 Decoder LIU Clock Rate Adapter 10.5.1.1 ...
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Line Loopback (LLB) Line loopback is enabled by setting PORT.CR4.LBM[2:0] = X10. DLB and LLB are enabled at the same time when LBM[2:0] = 110, and only LLB is enabled when LBM[2:0] = 010. The clock from the receive ...
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When the DS3 framed AIS signal is initiated or terminated, in addition to no BPV or CV errors, there should be no framing or P-bit (parity) or CP-bit errors introduced. The ...
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Figure 10-12 shows the AIS signal flow through the device. Figure 10-12. AIS Signal Flow 0 TRANSMIT LINE 1 LLB LINE/TRIBUTARY SIDE RECEIVE LINE Table 10-18 lists the LAIS decodes for various line AIS enable modes. Table 10-18. Line AIS ...
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Table 10-19 lists the PAIS decodes for various payload AIS enable modes. Table 10-19. Payload (Downstream) AIS Enable Modes PAIS[2:0] When AIS is sent PORT.CR1 000 Always 001 When LLB (no DLB) active 010 When PLB active 011 When LLB(no ...
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Table 10-20 to Table 10-22 describe the function selected by the FM bits and other pin mode bits for the multiplexed pins. Table 10-20. TSOFIn Input Pin Functions FM[2:0] PORT.CR2 Pin function 0XX (FSCT) TSOFIn 1XX (FBM) Not used Table ...
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Table 10-24. RCLKOn/RGCLKn Output Pin Functions FM[2:0] RCLKS PORT.CR2 PORT.CR3 0XX (FSCT) 0 0XX (FSCT) 1 1XX (FBM) X 10.5.9 Framing Modes The framing modes are selected independently of the line interface modes using the PORT.CR2.FM[2:0] control bits. Different blocks ...
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Table 10-26. Line Mode Select Bits LM[2:0] LINE.TCR.TZSD & LM[2:0] LINE.RCR.RZSD (PORT.CR2) 0 000 0 001 0 010 0 011 1 000 1 001 1 010 1 011 X 1XX Line Code LIU B3ZS/HDB3 OFF B3ZS/HDB3 ON B3ZS/HDB3 ON B3ZS/HDB3 ...
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DS3/E3 Framer / Formatter 10.6.1 General Description The Receive DS3/E3 Framer receives a unipolar DS3/E3 signal, determines frame alignment and extracts the DS3/E3 overhead in the receive direction. The Transmit DS3/E3 Formatter receives a DS3/E3 payload, generates framing, inserts ...
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Receive Framer • Programmable DS3 or E3 framer – Accepts a DS3 (M23 or C-bit (G.751 or G.832) signal and performs DS3/E3 overhead termination. • Arbitrary framing format support – Accepts a signal with an arbitrary framing ...
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Figure 10-14. DS3 Frame Format ...
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The multiframe framer checks for a multiframe boundary. When the multiframe framer identifies a multiframe boundary, it updates the data path frame counters if either an OOF or OOMF condition is present. The multiframe framer waits until a subframe boundary ...
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F-bits has been errored, or when the DS3 framer updates the data path frame counters. Multiframe alignment OOF is programmable (on or off). A Severely Errored Frame (SEF) condition is declared when ...
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P-bit parity errors are determined by calculating the parity of the current DS3 frame (payload bits only), and comparing the calculated parity to the P-bits (P match single P-bit parity error is declared ...
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X and X are the Remote Defect Indication (RDI) bits (also referred to as the far-end SEF/AIS bits the parity bits used for line error monitoring. M alignment bits the Application Identification Channel (AIC). C ...
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A FEBE error is generated by forcing the C inserted one error at a time, or continuously. The FEBE error insertion rate (single or continuous) is programmable. Each error type (framing, P-bit parity, C-bit parity, or FEBE) has a separate ...
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M23 DS3 Framer/Formatter 10.6.6.1 Transmit M23 DS3 Frame Processor The M23 DS3 frame format is shown in are the Remote Defect Indication (RDI) bits (also referred to as the far-end SEF/AIS bits). P bits used for line error monitoring. ...
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Transmit M23 DS3 Error Insertion Error insertion inserts various types of errors into the different DS3 overhead bits. The types of errors that can be inserted are framing errors and P-bit parity errors. The framing error insertion mode is ...
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Receive DS3 Downstream AIS Generation Downstream DS3 AIS (all ‘1’s) can be automatically generated on an OOF, LOS, or AIS condition or manually inserted. If automatic downstream AIS is enabled, downstream AIS is inserted when an LOS or AIS ...
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Single error insertion mode inserts an error at the next opportunity when requested. The multi-error insertion mode inserts the indicated number of errors at the next opportunities when requested, i.e., a single request will cause multiple errors to be inserted. ...
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A Receive Unframed All 1’s (RUA1) condition is declared if in each of 4 consecutive 2047 bit windows, five or less zeros are detected and an OOF condition is continuously present. A RUA1 condition is terminated if in each of ...
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Figure 10-18. G.832 E3 Frame Format FA1 FA2 Figure 10-19. MA Byte Format MSB 1 RDI REI RDI - Remote Defect Indicator REI - Remote Error Indicator SL - Signal Label MI ...
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FA1 and FA2 are the Frame Alignment bytes the Error Monitoring byte used for path error monitoring the Trail Trace byte used for end-to-end connectivity verification the Maintenance and Adaptation byte used for far-end ...
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FA1 and FA2 bytes respectively). Framing error(s) can be inserted one error at a time, or four consecutive frames. The framing error insertion mode (single or four) is programmable. The type of BIP-8 error(s) inserted is programmable (errored BIP-8 bit, ...
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A Loss Of Frame (LOF) condition is declared by the LOF integration counter when it has been active for a total of T ms. The LOF integration counter is active (increments count) when an OOF condition is present ...
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... Downstream AIS is removed when all OOF, LOS, and AIS conditions are terminated and manual downstream AIS insertion is disabled. RPDT will be forced to all ones during downstream AIS. STATUS 000 Match 001 Mismatch XXX Mismatch 000 Mismatch 001 Match XXX Match 000 Mismatch 001 Match XXX Match YYY Mismatch ≠ YYY 95 DS3171/DS3172/DS3173/DS3174 ...
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HDLC Overhead Controller 10.7.1 General Description The DS3174,3,2,1 devices contain built-in HDLC controllers (one per port) with 256 byte FIFOs for insertion/extraction of DS3 PMDL, G.751 Sn bit and G.832 NR/GC bytes. The HDLC Overhead Controller demaps HDLC overhead ...
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Transmit FIFO The Transmit FIFO block contains memory for 256 bytes of data with data status information and controller circuitry for reading and writing the memory. The Transmit FIFO controller functions include filling the memory, tracking the memory fill ...
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Receive HDLC Overhead Processor The Receive HDLC Overhead Packet Processor accepts data from the DS3/E3 Framer and performs packet delineation, inter-frame fill filtering, packet abort detection, destuffing, FCS processing, and bit reordering. If receive data inversion is enabled, the ...
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The Receive FIFO accepts data from the Receive Packet Processor until full packet start is received while full, the data is discarded and a FIFO overflow condition is declared. If any other packet data is received while full, ...
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Programmable trace ID multi-frame alignment – The transmit side can be programmed to perform trail trace multi-frame alignment insertion. The receive side can be programmed to perform trail trace multi-frame synchronization. • Programmable bit reordering – The trace identifier ...
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... The Receive Data Storage block contains memory for 48 bytes of data, maintains data status information, and has controller circuitry for reading and writing the memory. The Receive Data Storage controller functions include filling Bit 4 Bit 5 Bit 6 DT[4] DT[5] DT[6] Figure 10-22) of each trail trace identifier byte (The 101 DS3171/DS3172/DS3173/DS3174 Figure 10-22). The MAS bits are Bit 7 Bit 8 LSB DT[7] DT[8] ...
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The Receive Data Storage accepts data and data status from the Receive Trace ID Processor, stores the data in memory, and maintains data status information. The data is read from ...
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This is to differentiate between a code in a register and the corresponding code in a signal. 10.9.3.1 Transmit Data Storage The Transmit Data Storage block contains the registers for two FEAC codes ...
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Line Encoder/Decoder 10.10.1 General Description The B3ZS/HDB3 Decoder converts a bipolar signal to a unipolar signal in the receive direction. B3ZS/HDB3 Encoder converts a unipolar signal to a bipolar signal in the transmit direction. In the transmit direction, the ...
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HDB3 signature into the bipolar data stream if both the POS and NEG signals are zero for four consecutive clock periods. Zero suppression encoding can be disabled which will result in AMI-coded data. Error insertion is ...
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LOS condition, the first B3ZS/HDB3 signature to be detected will not depend upon the polarity of any BPV contained within the signature. Figure 10-26. B3ZS Signatures RLCLK (RX DATA) RPOS RNEG RLCLK (RX DATA) V RPOS RNEG Figure 10-27. HDB3 ...
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Immediately after a reset (or datapath reset LOS condition, a BPV will not be declared when the first valid one (RPOS high and RNEG low, or RPOS low and RNEG high) is received. Bipolar to unipolar conversion converts ...
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Table 10-31. Pseudorandom Pattern Generation PATTERN TYPE PTF[4:0] (hex O.153 (511 type O.152 and O.153 08 (2047 type O.151 O.153 O.151 QRSS ...
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Receive PRBS Synchronization PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and then checking the next ...
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Figure 10-30. Repetitive Pattern Synchronization State Diagram 1 bit error Verify Pattern Matches 10.11.4.3 Receive Pattern Monitoring Receive pattern monitoring monitors the incoming data stream for both an OOS condition and bit errors and counts the incoming bits. An Out ...
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LIU—Line Interface Unit 10.12.1 General Description The line interface units (LIUs) perform the functions necessary for interfacing at the physical layer to DS3 or E3 lines. Each LIU has independent receive and transmit paths and a built-in jitter attenuator. ...
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Detailed Description The receiver performs clock and data recovery from an alternate mark inversion (AMI) coded signal or a B3ZS- or HDB3-coded AMI signal and monitors for loss of the incoming signal. The transmitter drives standard pulse-shape waveforms onto ...
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The transmitter line driver can be disabled and the TXPn and TXNn outputs tri-stated by asserting the LTS configuration bit (PORT.CR2.LTS). Powering down the transmitter through the TPD configuration bit (CPU bus mode) also tri-states the TXPn and TXNn outputs. ...
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Table 10-34. Recommended Transformers MANUFACTURER PART Pulse Engineering PE-65968 Pulse Engineering PE-65969 TG07- Halo Electronics 0206NS TD07- Halo Electronics 0206NE Note: Table subject to change. Industrial temperature range and multiport transformers are also available. Contact the manufacturers for details at ...
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For E3 LOS Assertion: The ALOS detector in the AGC/equalizer block detects that the incoming signal is less than or equal to a signal level approximately 24dB below nominal, and mutes the data coming out of the clock and data ...
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... The register addresses of the global, test, and all four ports are concatenated to cover the address range of 000 to 7FF. The address map requires 11 bits of address, ADR[10:0]. The upper address bit A[10] is decoded for the DS3174 and DS3173 devices. The upper address bit A[10 not used by the DS3172 and DS3171 devices and must be tied low at the pin. ...
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Table 11-1. Global and Test Register Address Map ADDRESS 000–01F Global registers, Section 020–02F Unused 030–03F Reserved 040–1FF Port 1 Register Map 200–23F Test Registers 240–3FF Port 2 Register Map 400–43F Test Registers 440–5FF Port 3 Register Map 600–63F Unused ...
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Table 11-2. Per Port Register Address Map Port 1 Port 2 040 to 1FF 240 to 3FF ADDRESS DESCRIPTION OFFSET 040–05F Port common registers 060–07F BERT 080–08B Reserved 08C–08F B3ZS/HDB3 transmit line encoder 090–09F B3ZS/HDB3 receive line decoder 0A0–0AF HDLC ...
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REGISTER MAPS AND DESCRIPTIONS 12.1 Registers Bit Maps Note: In 8-bit mode, register bits[15:8] correspond to the upper byte, and register bits[7:0] correspond to the lower byte. For example, address 001h is the upper byte (bits [15:8]) and address ...
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Table 12-2. Port Register Bit Map Note: J and K are variable dependent upon port. Port 1 Port Address Register Type Bit 7 16-bit 8-bit J40 J40 RW PORT.CR1 J41 J42 J42 RW ...
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Address Register Type Bit 7 16-bit 8-bit J6C J6C R BERT.SR J6D J6E J6E RL BERT.SRL J6F J70 J70 RW BERT.SRIE J71 J72 J72 UNUSED J73 J74 J74 R BERT.RBECR1 J75 J76 J76 R BERT.RBECR2 J77 J78 J78 R BERT.RBCR1 ...
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HDLC Register Bit Map Table 12-5. HDLC Register Bit Map Address Register Type Bit 7 16-bit 8-bit JA0 JA0 RW HDLC.TCR JA1 JA2 JA2 RW HDLC.TFDR JA3 JA4 JA4 R HDLC.TSR JA5 JA6 JA6 RL HDLC.TSRL JA7 JA8 JA8 ...
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Address Register Type Bit 7 16-bit 8-bit JD0 JD0 RW FEAC.RCR JD1 JD2 JD2 UNUSED JD3 JD4 JD4 R FEAC.RSR JD5 JD6 JD6 RL FEAC.RSRL JD7 JD8 JD8 RW FEAC.RSRIE JD9 JDA JDA UNUSED JDB JDC JDC R FEAC.RFDR JDD ...
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T3 Register Bit Map Table 12-8. T3 Register Bit Map Address Register Type Bit 7 16-bit 8-bit K18 K18 RW T3.TCR K19 K1A K1A RW T3.TEIR K1B K1C- K1C RESERVED K1E K1F K20 K20 RW T3.RCR K21 K22 K22 ...
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Address Register Type Bit 7 16-bit 8-bit K20 K20 RW E3G751.RCR K21 K22 K22 RESERVED K23 K24 K24 R E3G751.RSR1 K25 K26 K26 R E3G751.RSR2 K27 K28 K28 E3G751.RSRL1 RL K29 K2A K2A E3G751.RSRL2 RL K2B K2C E3G751.RSRIE1 K2C RW ...
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Address Register Type Bit 7 16-bit 8-bit K2A K2A RL E3G832.RSRL2 K2B K2C K2C RW E3G832.RSRIE1 K2D K2E K2E RW E3G832.RSRIE2 K2F K30 K30 R E3G832.RMABR K31 K32 K32 R E3G832.RNGBR K33 K34 K34 R E3G832.RFECR K35 K36 K36 R ...
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Global Registers Table 12-12. Global Register Map Address Register 000h GL.IDR 002h GL.CR1 GL.CR2 004h 006h -- 008h -- 00Ah GL.GIOCR 00Ch -- 00Eh -- 010h GL.ISR 012h GL.ISRIE 014h GL.SR 016h GL.SRL GL.SRIE 018h 01Ah -- 01Ch GL.GIORR ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name GWRM INTM Default 0 0 Bit # 7 6 Name TMEI MEIMS Default 0 0 Bit 15: Global Write Mode (GWRM) This bit enables the global write mode. When ...
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Bit 0: Reset (RST). When this bit is set, all of the internal data path and status and control registers (except this RST bit), on all of the ports, will be reset to their default state. This bit must be ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name GPIO8S1 GPIO8S0 Default 0 0 Bit # 7 6 Name GPIO4S1 GPIO4S0 Default 0 0 Bits 15 to 14: General-Purpose IO 8 Select [1:0] (GPIO8S[1:0]). These bits determine the ...
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Output logic 1 Bits General-Purpose IO 1 Select [1:0] (GPIO1S[1:0]). These bits determine the function of the GPIO1 pin Input 01 = Port 1 A status output selected by PORT.CR4:GPIOA[3:0] in port control ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Bit # 7 6 Name -- -- Bit 1 : CLAD Loss of Lock (CLOL) – This bit is set when any of the PLLs in the ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name -- -- Default 0 0 Bit 2: One Second Interrupt Enable (ONESIE) This bit will drive the interrupt pin ...
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Per Port Common 12.3.1 Register Bit Descriptions Table 12-13. Per Port Common Register Map Address Register 40h PORT.CR1 (0,2,4,6) 42h PORT.CR2 (0,2,4,6) 44h PORT.CR3 (0,2,4,6) 46h PORT.CR4 (0,2,4,6) 48h -- (0,2,4,6) 4Ah PORT.INV1 (0,2,4,6) 4Ch PORT.INV2 (0,2,4,6) 4Eh -- ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name RESERVED PAIS2 Default 0 0 Bit # 7 6 Name TMEI MEIM Default 0 0 Bits 14 to 12: Payload AIS Select [2:0] (PAIS[2:0]). This bit controls when an ...
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This software bit is logically ORed with the inverted hardware signal RST and the GL.CR1.RST bit Normal operation 1 = Force all internal ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name P8KRS1 P8KRS0 Default 0 0 Bit 13: Receive Clock Output Select (RCLKS). This bit is used to select the ...
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Use output clocks for timing reference 1 = Use input clocks for timing reference Bit 1: Transmit Framer IO Signal Timing Select (TFTS). This bit controls the timing reference for the signals on the transmit framer interface IO ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name RESERVED RESERVED Default 0 0 Bit # 7 6 Name TOHI TOHCKI Default 0 0 Bit 12 : TSOFOn/TDENn/Invert (TSOFOI). This bit inverts the TSOFOn / TDENn pin when ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- RESERVED Default 0 0 Bit # 7 6 Name ROHI ROHCKI Default 0 0 Bit 12 : RSOFOn/RDENn Invert (RSOFOI). This bit inverts the RSOFOn / RDENn pin ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Bit # 7 6 Name TTSR FSR Bit 9: Port Status Register Interrupt Status (PSR) This bit is set when any of the latched status register bits, ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Bit # 7 6 Name -- -- Bit 2: Transmit Driver Monitor Status (TDM) This bits indicates the status of the transmit monitor circuit in the transmit ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Bit # 7 6 Name RLCLKA TCLKIA Bit 7: Receive Line Clock Activity Status Latched (RLCLKA) This bit will be set when the signal on the RLCLKn ...
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BERT 12.4.1 BERT Register Map The BERT utilizes 12 registers. Note: The BERT tegisters will be cleared when GL.CR1.RSTDP or PORT.CR1.RSTDP or PORT.CR1.PD is set. Table 12-14. BERT Register Map Address Register (0,2,4,6)60h BERT.CR (0,2,4,6)62h BERT.PCR (0,2,4,6)64h BERT.SPR1 (0,2,4,6)66h ...
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Bit 5: Receive New Pattern Load (RNPL) – A zero to one transition of this bit will cause the programmed test pattern (QRSS, PTS, PLF[4:0}, PTF[4:0], and BSP[31:0 loaded in to the receive pattern generator. This bit must ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name -- QRSS Default 0 0 Bits Pattern Tap Feedback (PTF[4:0]) – These five bits control the ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name BSP31 BSP30 Default 0 0 Bit # 7 6 Name BSP23 BSP22 Default 0 0 Bits BERT Seed/Pattern (BSP[31:16]) - Upper 16 bits of 32 bits. ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name -- -- Default 0 0 Bits Transmit Error Insertion Rate (TEIR[2:0]) – These three bits indicate ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Bit # 7 6 Name -- -- Bit 3: Performance Monitoring Update Status (PMS) – This bit indicates the status of the receive performance monitoring register (counters) ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name -- -- Default 0 0 Bit 3: Performance Monitoring Update Status Interrupt Enable (PMSIE) – This bit enables an ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name BEC23 BEC22 Default 0 0 Bits Bit Error Count (BEC[23:16]) - Upper 8-bits of Register. Bit ...
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B3ZS/HDB3 Line Encoder/Decoder 12.5.1 Transmit Side Line Encoder/Decoder Register Map The transmit side utilizes one register. Table 12-15. Transmit Side B3ZS/HDB3 Line Encoder/Decoder Register Map Address Register (0,2,4,6)8Ch LINE.TCR (0,2,4,6)8Eh -- 12.5.1.1 Register Bit Descriptions Register Name: Register Description: ...
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Receive Side Line Encoder/Decoder Register Map The receive side utilizes six registers. Table 12-16. Receive Side B3ZS/HDB3 Line Encoder/Decoder Register Map Address Register (0,2,4,6)90h LINE.RCR (0,2,4,6)92h (0,2,4,6)94h LINE.RSR (0,2,4,6)96h LINE.RSRL (0,2,4,6)98h LINE.RSRIE (0,2,4,6)9Ah (0,2,4,6)9Ch LINE.RBPVCR (0,2,4,6)9Eh LINE.REXZCR 12.5.2.1 Register ...
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BPV, and the first HDB3 signature is defined as two zeros followed by a BPV. All subsequent B3ZS/HDB3 signatures will be determined by the setting of this bit. Bit 0: Receive Zero Suppression Decoding ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name -- -- Default 0 0 Bit 5: Zero Suppression Code Detect Interrupt Enable (ZSCDIE) – This bit enables an ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name BPV15 BPV14 Default 0 0 Bit # 7 6 Name BPV7 BPV6 Default 0 0 Bits Bipolar Violation Count (BPV[15:0]) – These sixteen bits indicate the ...
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HDLC 12.6.1 HDLC Transmit Side Register Map The transmit side utilizes five registers. Table 12-17. Transmit Side HDLC Register Map Address Register (0,2,4,6)A0h HDLC.TCR (0,2,4,6)A2h HDLC.TFDR (0,2,4,6)A4h HDLC.TSR (0,2,4,6)A6h HDLC.TSRL (0,2,4,6)A8h HDLC.TSRIE (0,2,4,6)AAh -- (0,2,4,6)ACh -- (0,2,4,6)AEh -- 12.6.1.1 ...
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Bit 3: Transmit Bit Reordering Enable (TBRE) – When 0, bit reordering is disabled (The first bit transmitted is the LSB of the Transmit FIFO Data byte TFD[0]). When 1, bit reordering is enabled (The first bit transmitted is the ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Bit # 7 6 Name -- -- Bits Transmit FIFO Fill Level (TFFL[5:0]) – These six bits indicate the number of eight byte groups ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name -- -- Default 0 0 Bit 5: Transmit FIFO Overflow Interrupt Enable (TFOIE) – This bit enables an interrupt ...
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HDLC Receive Side Register Map The receive side utilizes five registers. Table 12-18. Receive Side HDLC Register Map Address Register (0,2,4,6)B0h HDLC.RCR (0,2,4,6)B2h -- (0,2,4,6)B4h HDLC.RSR (0,2,4,6)B6h HDLC.RSRL (0,2,4,6)B8h HDLC.RSRIE (0,2,4,6)BAh -- (0,2,4,6)BCh HDLC.RFDR (0,2,4,6)BEh -- 12.6.2.1 Register Bit ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Bit # 7 6 Name -- -- Bit 2: Receive FIFO Full (RFF) – When 0, the Receive FIFO contains 255 or less bytes of data. When ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name RFOIE -- Default 0 0 Bit 7: Receive FIFO Overflow Interrupt Enable (RFOIE) – This bit enables an interrupt ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name RFD7 RFD6 Default X X Bit # 7 6 Name -- -- Default 0 0 Note: The FIFO data and status are updated when the Receive FIFO Data (RFD[7:0]) ...
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FEAC Controller 12.7.1 FEAC Transmit Side Register Map The transmit side utilizes five registers. Table 12-19. FEAC Transmit Side Register Map Address Register (0,2,4,6)C0h FEAC.TCR (0,2,4,6)C2h FEAC.TFDR (0,2,4,6)C4h FEAC.TSR (0,2,4,6)C6h FEAC.TSRL (0,2,4,6)C8h FEAC.TSRIE (0,2,4,6)CAh -- (0,2,4,6)CCh -- (0,2,4,6)CEh -- ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name -- -- Default 0 0 Bits Transmit FEAC Code B (TFCB[5:0]) – These six bits are ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name -- -- Default 0 0 Bit 0: Transmit FEAC Idle Interrupt Enable (TFIIE) – This bit enables an interrupt ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Bit # 7 6 Name -- -- Bit 3: Receive FEAC FIFO Empty (RFFE) – When 0, the Receive FIFO contains at least one code. When 1, ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name -- -- Default 0 0 Bit 2: Receive FEAC FIFO Overflow Interrupt Enable (RFFOIE) – This bit enables an ...
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Trail Trace 12.8.1 Trail Trace Transmit Side The transmit side utilizes three registers. Register Map Table 12-21. Transmit Side Trail Trace Register Map Address Register (0,2,4,6)E8h TT.TCR (0,2,4,6)EAh TT.TTIAR (0,2,4,6)ECh TT.TIR (0,2,4,6)EEh -- 12.8.1.1 Register Bit Descriptions Register Name: ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name -- -- Default 0 0 Bits Transmit Trail Trace Identifier Address (TTIA[3:0]) – These four bits ...
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Trail Trace Receive Side Register Map The receive side utilizes seven registers. Table 12-22. Trail Trace Receive Side Register Map Address Register (0,2,4,6)F0h TT.RCR (0,2,4,6)F2h TT.RIAR (0,2,4,6)F4h TT.RSR (0,2,4,6)F6h TT.RSRL (0,2,4,6)F8h TT.RSRIE (0,2,4,6)FAh -- (0,2,4,6)FCh TT.RIR (0,2,4,6)FEh TT.EIR 12.8.2.1 ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name -- -- Default 0 0 Bits Expected Trail Trace Identifier Address (ETIA[3:0]) – These four bits ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Bit # 7 6 Name -- -- Bit 3: Receive Trail Trace Identifier Change Latched (RTICL) – This bit is set when the receive trail trace identifier ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name RTD7 RTD6 Default 0 0 Bits Receive Trail Trace Identifier Data (RTD[7:0]) – These eight bits ...
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DS3/E3 Framer 12.9.1 Transmit DS3 The transmit DS3 utilizes two registers. Table 12-23. Transmit DS3 Framer Register Map Address Register T3 Transmit Control Register (1,3,5,7)18h T3.TCR (1,3,5,7)1Ah T3.TEIR T3 Transmit Error Insertion Register (1,3,5,7)1Ch -- Reserved (1,3,5,7)1Eh -- Reserved ...
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Bit 2: Automatic RDI Defeat (ARDID) – When 0, the RDI is automatically generated based received DS3 alarms. When 1, the RDI is inserted from the register bit TRDI. Bit 1: Transmit Frame Generation Control (TFGC) – When this bit ...
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Bit 1: Transmit Single Error Insert (TSEI) – This bit causes an error of the enabled type( inserted in the transmit data stream if manual error insertion is disabled (MEIMS = 0 transition causes ...
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Bit 13: Multi-frame Alignment OOF Disable (MAOD) – When 0, an OOF condition is declared whenever an OOMF or SEF condition is declared. When 1, an OOF condition is declared only when an SEF condition is declared. Bit 12: Manual ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name Reserved Reserved Bit # 7 6 Name OOMF SEF Bit 11: T3 Framing Format Mismatch (T3FM) – This bit indicates the DS3 framer is programmed for a framing format ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Bit # 7 6 Name -- -- Bit 3: C-bit Parity Error Count (CPEC) – When 0, the C-bit parity error count is zero. When 1, the ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Bit # 7 6 Name -- -- Bit 11: C-bit Parity Error Latched (CPEL) – This bit is set when a C-bit parity error is detected. This ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name Reserved Reserved Default 0 0 Bit # 7 6 Name OOMFIE SEFIE Default 0 0 Bit 11: T3 Framing Format Mismatch Interrupt Enable (T3FMIE) – This bit enables an ...
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Bit 2: Alarm Indication Signal Interrupt Enable (AISIE) – This bit enables an interrupt if the AISL bit is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set interrupt disabled 1 = interrupt enabled ...
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Bit 2: Far-End Block Error Count Interrupt Enable (FBECIE) – This bit enables an interrupt if the FBECL bit is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set interrupt disabled 1 = interrupt ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name FBE15 FBE14 Default 0 0 Bit # 7 6 Name FBE7 FBE6 Default 0 0 Bits Far-End Block Error Count (FBE[15:0]) – These sixteen bits indicate ...
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Transmit G.751 E3 The transmit G.751 E3 utilizes two registers. 12.9.3.1 Register Map Table 12-25. Transmit G.751 E3 Framer Register Map Address Register (1,3,5,7)18h E3G751.TCR (1,3,5,7)1Ah E3G751.TEIR (1,3,5,7)1Ch -- (1,3,5,7)1Eh -- 12.9.3.2 Register Bit Descriptions Register Name: Register Description: ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name Reserved Reserved Default 0 0 Bits Framing Error Insert Control (FEIC[1:0]) – These two bits control ...
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Receive G.751 E3 Register Map The receive G.751 E3 utilizes eight registers. Table 12-26. Receive G.751 E3 Framer Register Map Address Register (1,3,5,7)20h E3G751.RCR (1,3,5,7)22h -- (1,3,5,7)24h E3G751.RSR1 (1,3,5,7)26h E3G751.RSR2 E3G751.RSRL1 (1,3,5,7)28h (1,3,5,7)2Ah E3G751.RSRL2 (1,3,5,7)2Ch E3G751.RSRIE1 (1,3,5,7)2Eh E3G751.RSRIE2 (1,3,5,7)30h ...
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Bits Framing Error Count Control (FECC[1:0]) – These two bits control the type of framing error events that are counted count OOF occurrences (counted regardless of the setting of the ECC bit).. 01 = count ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name Reserved Reserved Bit # 7 6 Name RAB RNB Bit 8: Receive Unframed All 1’s (RUA1) – When 0, the receive frame processor is not in a receive unframed ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name Reserved Reserved Bit # 7 6 Name ACL NCL Bit 8: Receive Unframed All 1’s Change Latched (RUA1L) – This bit is set when the RUA1 bit changes state. ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name Reserved Reserved Default 0 0 Bit # 7 6 Name ACIE NCIE Default 0 0 Bit 8: Receive Unframed All 1’s Interrupt Enable (RUA1IE) – This bit enables an ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name -- -- Default 0 0 Bit 8: Framing Error Interrupt Enable (FEIE) – This bit enables an interrupt if ...
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Transmit G.832 E3 Register Map The transmit G.832 E3 utilizes four registers. Table 12-27. Transmit G.832 E3 Framer Register Map Address Register (1,3,5,7)18h E3G832.TCR (1,3,5,7)1Ah E3G832.TEIR (1,3,5,7)1Ch E3G832.TMABR (1,3,5,7)1Eh E3G832.TNGBR 12.9.5.1 Register Bit Descriptions Register Name: Register Description: Register ...
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Bit 1: Transmit Frame Generation Control (TFGC) – When this bit is zero, the Transmit Frame Processor frame generation is enabled. The E3 overhead positions in the incoming E3 payload will be overwritten with the internally generated DS3 overhead. When ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name TPT2 TPT1 Default 0 0 Bits Transmit Payload Type (TPT[2:0]) – These bits determines the value ...
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Receive G.832 E3 Register Map The receive G.832 E3 utilizes thirteen registers. Table 12-28. Receive G.832 E3 Framer Register Map Address Register (1,3,5,7)20h E3G832.RCR (1,3,5,7)22h E3G832.RMACR (1,3,5,7)24h E3G832.RSR1 (1,3,5,7)26h E3G832.RSR2 E3G832.RSRL1 (1,3,5,7)28h (1,3,5,7)2Ah E3G832.RSRL2 (1,3,5,7)2Ch E3G832.RSRIE1 (1,3,5,7)2Eh E3G832.RSRIE2 (1,3,5,7)30h ...
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OOF or AIS condition is terminated, and the next E3 frame. When 1, framing errors, parity errors, and REI errors will be counted regardless of the presence of an OOF or AIS condition. Bits Framing Error ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name Reserved -- Bit # 7 6 Name Reserved Reserved Bit 12: Receive Payload Type Unstable (RPTU) – When 0, the receive payload type is stable. When 1, the receive ...