DS32506NW Maxim Integrated, DS32506NW Datasheet
DS32506NW
Specifications of DS32506NW
Related parts for DS32506NW
DS32506NW Summary of contents
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GENERAL DESCRIPTION The DS32506 (6 port), DS32508 (8 port), and DS32512 (12 port) line interface units (LIUs) are highly integrated, low-power, feature-rich LIUs for DS3, E3, and STS-1 applications. Each LIU port in these devices has independent receive ...
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STANDARDS COMPLIANCE .............................................................................................6 2. BLOCK DIAGRAM ..............................................................................................................7 3. APPLICATION EXAMPLE ..................................................................................................8 4. DETAILED DESCRIPTION..................................................................................................9 5. DETAILED FEATURES.....................................................................................................11 5 .......................................................................................................................11 LOBAL EATURES 5.2 R .....................................................................................................................................11 ECEIVER 5.3 T ...............................................................................................................................11 RANSMITTER 5 .....................................................................................................................11 ITTER TTENUATOR 5.5 B ...
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Configuration and Monitoring.............................................................................................................. 36 8.5.2 Receive Pattern Detection .................................................................................................................. 37 8.5.3 Transmit Pattern Generation............................................................................................................... 39 8.6 L ..................................................................................................................................40 OOPBACKS 8 ....................................................................................................................40 LOBAL ESOURCES 8.7.1 Clock Rate Adapter (CLAD)................................................................................................................ 40 8.7.2 One-Second Reference Generator ..................................................................................................... 41 8.7.3 General-Purpose ...
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Figure 2-1. Block Diagram ........................................................................................................................................... 7 Figure 3-1. 12-Port Unchannelized DS3/E3 Card ....................................................................................................... 8 Figure 4-1. External Connections, Internal Termination Enabled................................................................................ 9 Figure 4-2. External Connections, Internal Termination Disabled............................................................................. 10 Figure 8-1. DS3 Waveform Template ........................................................................................................................ 27 Figure 8-2. STS-1 ...
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Table 1-1. Applicable Telecommunications Standards ............................................................................................... 6 Table 7-1. Short Pin Descriptions .............................................................................................................................. 14 Table 7-2. Analog Line Interface Pin Descriptions .................................................................................................... 17 Table 7-3. Digital Framer Interface Pin Descriptions................................................................................................. 17 Table 7-4. Global Pin Descriptions ............................................................................................................................ 18 Table 7-5. ...
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STANDARDS COMPLIANCE Table 1-1. Applicable Telecommunications Standards SPECIFICATION T1.102-1993 Digital Hierarchy—Electrical Interfaces T1.231-2003 Digital Hierarchy—Layer 1 In-Service Digital Transmission Performance Monitoring T1.404-2002 Network-to-Customer Installation—DS3 Metallic Interface Specification TR54014 ACCUNET® T45 Service Description and Interface Specification, 05/92 Business TeleCommunications; 34Mbps ...
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BLOCK DIAGRAM Figure 2-1. Block Diagram RXPn Pre-Amp Equalizer, RXNn and CDR ARES Driver TDMn Monitor TXPn Line TXNn Driver shaping CLAD AGC, B3ZS/ HDB3 Decoder ALB JA LLB B3ZS/ Wave- HDB3 Encoder Parallel and SPI Bus Interfaces 7 ...
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APPLICATION EXAMPLE Figure 3-1. 12-Port Unchannelized DS3/E3 Card DS3/E3/STS-1 DS32512 DS31912 77.76MHz TELECOM BUS 12-PORT 12-PORT DS3/E3/STS-1 LIU MAPPER 8 of 130 DS32506/DS32508/DS32512 ...
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DETAILED DESCRIPTION The DS32506 (6 port), DS32508 (8 port), and DS32512 (12 port) LIUs perform the functions necessary for interfacing at the physical layer to DS3, E3, or STS-1 lines. Each LIU has independent receive and transmit paths and ...
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Figure 4-2. External Connections, Internal Termination Disabled 1:1 1:1 Shorthand Notations. The notation “DS325xx” throughout this data sheet refers to either the DS32506, DS32508, or DS32512. This data sheet is the specification for all three devices. The LIUs on the ...
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DETAILED FEATURES 5.1 Global Features Three interface modes: hardware, 8-/16-bit parallel bus, and SPI serial bus Independent per-port operation (e.g., line rate, jitter attenuator placement, or loopback type) Clock, data, and control signals can be inverted to allow a ...
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Bit Error-Rate Tester (BERT) Features One BERT per port Software programmable for insertion toward the transmit line interface or the receive system interface Generates and detects pseudo-random patterns of length 2 32 bits in length Large 24-bit error counter ...
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CONTROL INTERFACE MODES The DS325xx devices can be controlled by hardware interface, by microprocessor interface combination of both interfaces at the same time. The hardware interface is configured (enabled or disabled) independently from the microprocessor interface ...
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PIN DESCRIPTIONS Note: All digital pins are I/O pins in JTAG mode. This feature is to increase the effectiveness of board-level ATPG patterns to isolate interconnect failures. 7.1 Short Pin Descriptions n = port number ( for ...
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NAME TYPE RPD Ipd Receive Power-Down (All Ports) JAD[1:0] Ipd Jitter Attenuator Depth (All Ports) JAS[1:0] Ipd Jitter Attenuator Select (Tx, Rx, or Disabled) (Port n) LBn[1:0] I Loopback Control (Port n) LBS Ipd Loopback Select (all ports) 8-/16-BIT PARALLEL ...
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NAME TYPE RVSSn P Receive Ground (Port n) Transmit 1.8V Power, 1.8V ±5% (Port n) TVDDn P TVSSn P Transmit Ground (Port n) CLAD 1.8V ±5% CVDD P CVSS P CLAD Ground MANUFACTURING TEST MT[10:0] Test Manufacturing Test Pins DS32506/DS32508/DS32512 ...
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Detailed Pin Descriptions n = port number ( for DS32512 for DS32508 for DS32506 input, Ipu = input with internal pullup resistor, Ipd = input with internal pulldown resistor, ...
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Table 7-4. Global Pin Descriptions NAME TYPE Microprocessor Interface Select. When no microprocessor interface is selected, all microprocessor interface inputs are ignored and internally pulled low, and all microprocessor interface outputs are put in a high-impedance state. See Section 000 ...
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Table 7-5. Hardware Interface Pin Descriptions NAME TYPE LIU Mode Control (Port n). When only the hardware interface is enabled HW = 1), these pins set the LIU mode for port n. See Section 8. DS3 LMn[1:0] Ipd ...
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NAME TYPE Internal Termination Resistance Enable (Tx and Rx) (All Ports). This bit indicates when the internal termination is enabled. See Section 8.2.8. ITRE Disabled. The transmitters and receivers are terminated externally Enabled. The transmitters ...
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Table 7-6. Parallel Interface Pin Descriptions NAME TYPE Chip Select (Active Low). This pin must be asserted to read or write internal registers. See CS I Section 8.8.3. Read Enable (Active Low)/Data Strobe (Active Low For the Intel-style ...
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Table 7-7. SPI Serial Interface Pin Descriptions NAME TYPE Chip Select (Active Low). This pin must be asserted to read or write internal registers See Section 8.9. Serial Clock. SCLK is always driven by the SPI bus master. ...
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Table 7-9. JTAG Pin Descriptions NAME TYPE JTAG Clock. This pin shifts data into JTDI on the rising edge and out of JTDO on the JTCLK I falling edge. JTCLK is typically a low frequency (less than 10MHz) 50% duty ...
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FUNCTIONAL DESCRIPTION 8.1 LIU Mode Each port is independently configurable for DS3 STS-1 operation. When only the hardware interface is enabled (IFSEL = 000 and HW = 1), the ≠ 000) the PORT.CR2:LM[1:0] control bits specify the ...
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BPV in the last B3ZS/HDB3 codeword. The first 1 is transmitted according to the normal AMI rule, but the second 1 is transmitted with the same ...
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Driver Monitor and Output Failure Detection The transmit driver monitor compares the amplitude of the transmit waveform to thresholds V the amplitude is less than V TXMIN activates the TDM output pin (if the hardware interface is enabled) and ...
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Figure 8-1. DS3 Waveform Template 1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 -1.0 -0.75 Table 8-2. DS3 Waveform Equations TIME (IN UNIT INTERVALS) -0.85 ≤ T ≤ -0.68 -0.68 ≤ T ≤ +0.36 0.36 ≤ T ≤ 1.4 -0.85 ...
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Figure 8-2. STS-1 Waveform Template 2nd Rise 1.2 1st Rise 1.0 0.8 0.6 0.4 0.2 0 -0.2 -1.0 -0.75 -0.5 -0.25 Table 8-4. STS-1 Waveform Equations TIME (IN UNIT INTERVALS) -0.85 ≤ T ≤ -0.68 -0.68 ≤ T ≤ +0.26 ...
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Figure 8-3. E3 Waveform Template Zero Level Overshoot 1.2 1.1 1.0 0.9 0.8 0.6 0.5 0.4 0.2 0.1 0 -0.1 -0.2 -15 -10 Table 8-6. E3 Waveform Test Parameters and Limits PARAMETER Rate Line Code Transmission Medium Test Measurement Point ...
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Receiver 8.3.1 Interfacing to the Line The receiver can be transformer-coupled or capacitor-coupled to the line. Typically, the receiver interfaces to the incoming coaxial cable (75 Ω ) through a 1:1 isolation transformer. The receive line termination can be ...
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The AGC and the equalizer work simultaneously but independently to supply a signal of nominal amplitude and pulse shape to the clock and data recovery block. The AGC/equalizer block automatically handles direct (0 meters) monitoring of ...
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The DLOS detector supports the requirements of ANSI T1.231 for STS-1 LOS defects. At the STS-1 rate, the time required for the DLOS detector to count 192 consecutive zeros falls in the range of 2.3 ≤ T ≤ 100 μ ...
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When L INE.RCR:E3CVE = 0: 8 – A BPV immediately preceded by a valid pulse (B, V). – A BPV with the same polarity as the last BPV. – The third zero in an EXZ. When L INE.RCR:E3CVE = 1: ...
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Jitter and Wander Tolerance The receiver exceeds the input jitter tolerance requirements of all applicable telecommunication standards in 1-1. See Figure 8-4 for STS-1 and E3 jitter tolerance characteristics. See characteristics. See Figure 8-6 for DS3 and E3 wander ...
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Figure 8-6. DS3 and E3 Wander Tolerance 1000 805 137.5 100 67 34.4 10 1.2 6. 8.3.10 Jitter Transfer Without the jitter attenuator on the receive side, the receiver attenuates jitter at frequencies above its corner frequency ...
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Figure 8-7. Jitter Attenuation/Jitter Transfer 21.7 Hz (DS3) 16.7 Hz (E3) 27Hz 25.2 Hz (STS -1) 40Hz 0 -10 DS325xx DS3/E3/STS-1 MINIMUM JITTER ATTENUATION -20 WITH JITTER ATTENUATOR ENABLED -30 10 8.5 BERT Each LIU port has a built-in bit ...
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Table 8-9. Pseudorandom Pattern Generation PATTERN TYPE PTF[4:0] (hex O.153 (511 type O.152 and 08 O.153 (2047 type O.151 O.153 O.151 QRSS ...
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Receive PRBS Synchronization PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and then checking the next ...
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Figure 8-9. Repetitive Pattern Synchronization State Diagram Sync 1 bit error Verify Pattern Matches 8.5.2.3 Receive Pattern Monitoring Receive pattern monitoring monitors the incoming data stream for both an OOS condition and bit errors and counts the incoming bits. An ...
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Transmit Error Insertion Errors can be inserted into the generated pattern one at a time rate of one out of every programmable ( off) in the BERT.TEICR:TEIR[2:0] configuration field. Single ...
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Table 8-11. CLAD Clock Source Settings CLAD[6:4] REFCLK 000 Don't Care 001 DS3 input 010 E3 input 011 STS-1 input 100 77.76MHz input 101 19.44MHz input 110 38.88MHz input 111 12.80MHz input Table 8-12. CLAD Clock Pin Output Settings CLAD[3:0]* ...
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General-Purpose I/O Pins When a microprocessor interface is enabled available per port, each of which can be used as a general-purpose input, general-purpose output, or loss-of-signal output. In addition, GPIOB1, GPIOB2, and GPIOB3 can be used as a global ...
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The PMS has an associated latched status bit that can generate an interrupt if enabled. The port PMS signal does not go high until an update of all the appropriately configured block-level performance monitoring counters in the port ...
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Clear-On-Read And Clear-On-Write Modes The latched status register bits can be programmed to clear on a read access or clear on a write access. The global control register bit GLOBAL.CR2.LSBCRE specifies the method used to clear all of the ...
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DS325xx continues to write the data received and increment its address counter. After the address counter reaches 7FFh it rolls over to address 000h and continues to increment. Burst Reads. See Figure 8-11. After The DS325xx ...
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Figure 8-11. SPI Bus Transactions Single-Byte Write CS R/W Register Address Burst SDI 0 (Write) SDO Single-Byte Read CS R/W Register Address Burst SDI 1 (Read) SDO Burst Write CS R/W Register Address Burst Data Byte 1 SDI 0 (Write) ...
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Figure 8-12. Interrupt Signal Flow PORT LATCHED STATUS REGISTER AND INTERRUPT ENABLE REGISTER PORT.SRL bit PORT.SRIE bit PORT.SRL bit PORT.SRIE bit block SRL bit block SRIE bit block SRL bit block SRIE bit BLOCK LATCHED STATUS REGISTER AND INTERRUPT ENABLE ...
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Table 8-16. Reset and Power-Down Sources REGISTER BITS PIN GLOBAL.CR1 PORT.CR1 RST RST RSTDP RST TPD RPD RSTDP ...
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REGISTER MAPS AND DESCRIPTIONS 9.1 Overview When a microprocessor interface is enabled accessible. The overall memory map is shown in of 000 to 7FFh. On the DS32508, writes in the address space for LIUs 9 through 12 are ignored, ...
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Overall Register Map Table 9-1. Overall Register Map BASE BLOCK ADDRESS 000h Global Registers 080h Port Registers 100h Port Registers for Port 2 180h Port Registers for Port 3 200h Port Registers for Port 4 280h Port Registers for ...
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Global Registers Table 9-3. Global Register Map ADDRESS REGISTER OFFSET 000h GLOBAL.IDR 002h GLOBAL.CR1 004h GLOBAL.CR2 006h–00Eh — 010h GLOBAL.GIOACR1 012h GLOBAL.GIOACR2 014h GLOBAL.GIOBCR1 016h GLOBAL.GIOBCR2 018h–01Eh — 020h GLOBAL.ISR 022h GLOBAL.ISRIE 024h–026h — 028h GLOBAL.SR 02Ah GLOBAL.SRL 02Ch ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name — — Default — 0 Bit # 7 6 Name TMEI MEIMS Default 0 0 Bits Global One-Second Reference Source (G1SRS[3:0]). These bits determine the source ...
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Bit 3: Global Performance Monitor Register Update (GPMU). When GLOBAL.CR1:GPM[1:0] = 00, this bit is used to update all of the performance monitor registers where block-level PMUM = 1 and PORT.CR1:PMUM = 1. When this bit transitions from low to ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name — Default — 0 Bit # 7 6 Name — — Default 0 0 Bits CLAD I/O Mode (CLAD[6:0]). These bits control the CLAD clock I/O ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name GIOA8S[1:0] Default 0 0 Bit # 7 6 Name GIOA4S[1:0] Default 0 0 Note: See Section 8.7.3 for more information. Bits 15, 14: General-Purpose I Select (GIOA8S[1:0]). ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name — — Default 0 0 Bit # 7 6 Name GIOA12S[1:0] Default 0 0 Note: See Section 8.7.3 for more information. Bits 7, 6: General-Purpose I Select ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name GIOB8S[1:0] Default 0 0 Bit # 7 6 Name GIOB4S[1:0] Default 0 0 Note: See Section 8.7.3 for more information. Bits 15, 14: General-Purpose I Select (GIOB8S[1:0]). ...
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Bits 1, 0: General-Purpose I Select (GIOB1S[1:0]). These bits specify the function of the GPIOB1 pin. Note: If GLOBAL.CR1:GPM[1:0] is set to 01, GPIOB1 is the global performance monitoring update input signal Input 01 = Output ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name — — Bit # 7 6 Name P7ISR P6ISR Bits Port n Interrupt Status Register (PnISR). This bit is set when any of the bits in ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name — — Default — — Bit # 7 6 Name — — Default — — Bit 2: CLAD Loss of Lock (CLOL). This bit is set when the CLAD ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name — — Default 0 0 Bit # 7 6 Name — — Default 0 0 Bit 2: CLAD Loss of Lock Interrupt Enable (CLOLIE). This bit is the interrupt ...
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Port Common Registers Table 9-4. Port Common Register Map ADDRESS REGISTER OFFSET 00h PORT.CR1 Port Control Register 1 02h PORT.CR2 Port Control Register 2 04h PORT.CR3 Port Control Register 3 06h — Unused 08h — Unused 0Ah PORT.INV Port ...
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Bit 3: Transmit Power-Down (TPD). When this bit is set, the transmit path of the port is powered down and considered “out of service”. The digital logic is powered down by stopping the clocks. See Section 8.11 Normal ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name — — Default 0 0 Bit # 7 6 Name LM[1:0] Default 0 0 Bits 7 and 6: LIU Mode (LM[1:0]). These bits select the operating mode of the ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name — — Default 0 0 Bit # 7 6 Name SCRD — Default 0 0 Bit 9: BERT Enable (BERTE). See Section 8. disable the BERT pattern ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name — — Default 0 0 Bit # 7 6 Name — TNEGI Default 0 0 Bit 6: TNEG Invert (TNEGI). This bit inverts the 0 = Noninverted 1 = ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name — — Bit # 7 6 Name — — Bit 3: Line Decoder Status Register Interrupt Status (LDSR). This bit is set when any of the latched status register ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name — — Default — — Bit # 7 6 Name — — Default — — Bit 0: Performance Monitoring Update Status (PMS). This bit is set when the PMS ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name — — Default 0 0 Bit # 7 6 Name — — Default 0 0 Bit 8: Transmit Clock Activity Latched Status Interrupt Enable (TCLKIE). This bit is the ...
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LIU Registers ADDRESS REGISTER OFFSET 20h LIU.CR1 22h LIU.CR2 24h LIU.TWSCR1 26h LIU.TWSCR2 28h LIU.SR 2Ah LIU.SRL 2Ch LIU.SRIE 2Eh LIU.RGLR Register Name: LIU.CR1 Register Description: LIU Control Register 1 Register Address 80h + 20h Bit # ...
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Bits 2, 0: Transmit Resistor Adjustment (TRESADJ[2:0]). These bits are used to adjust the internal termination resistance of the transmitter. See Section 8.2.8. 000 = 75 Ω 001 = 82 Ω 010 = 90 Ω 011 = 100 Ω 100 ...
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Register Name: LIU.TWSCR1 Register Description: LIU Transmit Waveshaping Control Register 1 Register Address 80h + 24h Bit # 15 14 Name Default 0 0 Bit # 7 6 Name Default 0 0 See Figure 8-1, Figure 8-2, and ...
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Bits 5, 4: Transmit Waveshaping Control (TWSC[5:4]). In DS3 and STS-1 modes, this field adjusts the amplitude of the second of two rising-edge segments mode this field has no effect, except for the 11 value, which is a ...
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Register Name: LIU.TWSCR2 Register Description: LIU Transmit Waveshaping Control Register 2 Register Address 80h + 26h Bit # 15 14 Name — — Default 0 0 Bit # 7 6 Name — — Default 0 0 Bits 3 ...
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Register Name: LIU.SR Register Description: LIU Status Register Register Address 80h + 28h Bit # 15 14 Name — — Default 0 0 Bit # 7 6 Name — — Default 1 1 Bit 10: Transmit Driver Monitor ...
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Register Name: LIU.SRL Register Description: LIU Status Register Latched Register Address 80h + 2Ah Bit # 15 14 Name — — Default 0 0 Bit # 7 6 Name — — Default 0 0 Bit 12: Jitter Attenuator ...
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Register Name: LIU.SRIE Register Description: LIU Status Register Interrupt Enable Register Address 80h + 2Ch Bit # 15 14 Name — — Default 0 0 Bit # 7 6 Name — — Default 0 0 Bit 12: Jitter ...
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Bit 0: Analog Loss Of Signal Interrupt Enable (ALOSIE). This bit is the interrupt enable for the LIU.SRL:ALOSL bit interrupt disabled 1 = interrupt enabled Register Name: LIU.RGLR Register Description: LIU Receive Gain Level Register Register Address: n ...
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B3ZS/HDB3 Encoder Registers ADDRESS REGISTER OFFSET 30h LINE.TCR 32h–3Eh — Register Name: LINE.TCR Register Description: B3ZS/HDB3 Transmit Control Register Register Address 80h + 30h Bit # 15 14 Name — — Default 0 0 Bit # 7 ...
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B3ZS/HDB3 Decoder Registers ADDRESS REGISTER OFFSET 40h LINE.RCR 42h — 44h LINE.RSR 46h LINE.RSRL 48h LINE.RSRIE 4Ah — 4Ch LINE.RBPVCR 4Eh LINE.REXZCR Register Name: LINE.RCR Register Description: B3ZS/HDB3 Receive Control Register Register Address 80h + 40h Bit ...
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Register Name: LINE.RSR Register Description: B3ZS/HDB3 Receive Status Register Register Address 80h + 44h Bit # 15 14 Name — — Default 0 0 Bit # 7 6 Name — — Default 0 0 Bit 3: Excessive Zero ...
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Register Name: LINE.RSRIE Register Description: B3ZS/HDB3 Receive Status Register Interrupt Enable Register Address 80h + 48h Bit # 15 14 Name — — Default 0 0 Bit # 7 6 Name — — Default 0 0 Bit 5: ...
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Register Name: LINE.RBPVCR Register Description: B3ZS/HDB3 Receive Bipolar Violation Count Register Register Address 80h + 4Ch Bit # 15 14 Name Default 0 0 Bit # 7 6 Name Default 0 0 Bits Bipolar Violation ...
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BERT Registers ADDRESS REGISTER OFFSET 50h BERT.CR 52h BERT.PCR 54h BERT.SPR1 56h BERT.SPR2 58h BERT.TEICR 5Ah — 5Ch BERT.SR 5Eh BERT.SRL 60h BERT.SRIE 62h — 64h BERT.RBECR1 66h BERT.RBECR2 68h BERT.RBCR1 6Ah BERT.RBCR2 6Ch — 6Eh — Register Name: ...
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Bit 4: Receive Pattern Inversion Control (RPIC) . See Section 8.5. not invert the incoming data stream 1 = invert the incoming data stream Bit 3: Manual Pattern Resynchronization (MPR). A zero-to-one transition of this bit causes ...
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Register Name: BERT.SPR1 Register Description: BERT Seed/Pattern Register #1 Register Address 80h + 54h Bit # 15 14 Name Default 0 0 Bit # 7 6 Name Default 0 0 Bits BERT Seed/Pattern (BSP[15:0]) Register ...
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Register Name: BERT.TEICR Register Description: BERT Transmit Error Insertion Control Register Register Address 80h + 58h Bit # 15 14 Name — — Default 0 0 Bit # 7 6 Name — — Default 0 0 Bits 5 ...
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Register Name: BERT.SR Register Description: BERT Status Register Register Address 80h + 5Ch Bit # 15 14 Name — — Default 0 0 Bit # 7 6 Name — — Default 0 0 Bit 3: Performance Monitoring Update ...
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Register Name: BERT.SRIE Register Description: BERT Status Register Interrupt Enable Register Address 80h + 60h Bit # 15 14 Name — — Default 0 0 Bit # 7 6 Name — — Default 0 0 Bit 3: Performance ...
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Register Name: BERT.RBECR2 Register Description: BERT Receive Bit Error Count Register #2 Register Address 80h + 66h Bit # 15 14 Name — — Default 0 0 Bit # 7 6 Name Default 0 0 Bits 7 to ...
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JTAG INFORMATION The DS325xx LIUs support the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The devices contain the following items, which meet the requirements set by the IEEE 1149.1 Standard ...
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ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Input or Output Lead with Respect to V Supply Voltage Range with Respect to V VDD33………………………………………………………………………………………………...-0.3V to +3.63V VDD18 ………………………………………………………………………………………………..-0.1V to +1.89V Ambient Operating Temperature Range*..…………………………………………………………………..-40°C to +85°C Junction Operating ...
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Table 11-2. DC Characteristics (VDD18 = 1.8V ±5%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, T PARAMETER Supply Current, VDD18 (Note 1) Supply Current, VDD33 (Note 1) Supply Current, Transmitters Disabled (All TOE = 0), VDD18 (Note 2) Supply ...
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Table 11-3. Framer Interface Timing (VDD18 = 1.8V ±5%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, T and Figure 11-2.) PARAMETER RCLK/TCLK Clock Period RCLK Duty Cycle TCLK Duty Cycle LIU Reference Clock Duty Cycle TPOS/TDAT, TNEG to TCLK ...
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Figure 11-1. Transmitter Framer Interface Timing Diagram TCLK (NORMAL) TCLK (INVERTED TPOS/TDAT TNEG Figure 11-2. Receiver Framer Interface Timing Diagram RCLK (NORMAL) RCLK (INVERTED) t7 RPOS/RDAT RNEG/RLCV ...
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Table 11-4. Receiver Input Characteristics—DS3 and STS-1 Modes (VDD18 = 1.8V ±5%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, T PARAMETER Receive Sensitivity (Length of Cable) Signal-to-Noise Ratio, Interfering Signal Test (Notes 1, 2) Input Pulse Amplitude, RMON = ...
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Table 11-6. Transmitter Output Characteristics—DS3 and STS-1 Modes (VDD18 = 1.8V ±5%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, T PARAMETER DS3 Output Pulse Amplitude, TLBO = 0 (Note 1) DS3 Output Pulse Amplitude, TLBO = 1 (Note 1) ...
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Table 11-8. Parallel CPU Interface Timing (VDD18 = 1.8V ±5%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, T (See Figure 11-3, Figure 11-4, Figure Figure 11-10.) PARAMETER RD Setup Time for A[10:0] Valid Setup Time ...
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Figure 11-3. Parallel CPU Interface Intel Read Timing Diagram (Nonmultiplexed) t1 A[10: D[15:0] RDY Figure 11-4. Parallel CPU Interface Intel Write Timing Diagram (Nonmultiplexed) t1 A[10: D[15:0] RDY t2 t3a t16 t3b t2 t6a ...
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Figure 11-5. Parallel CPU Interface Motorola Read Timing Diagram (Nonmultiplexed) t1 A[10:0] R D[15:0] RDY Figure 11-6. Parallel CPU Interface Motorola Write Timing Diagram (Nonmultiplexed) t1 A[10:0] R D[15:0] RDY t2 t3a t16 t3b t2 t6a ...
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Figure 11-7. Parallel CPU Interface Intel Read Timing Diagram (Multiplexed) t13 ALE t11 t12 A[10:0] t14 D[15:0] RDY Figure 11-8. Parallel CPU Interface Intel Write Timing Diagram (Multiplexed) t13 ALE t11 t12 A[10:0] t14 ...
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Figure 11-9. Parallel CPU Interface Motorola Read Timing Diagram (Multiplexed) t13 ALE t11 t12 A[10:0] t14 R D[15:0] RDY Figure 11-10. Parallel CPU Interface Motorola Write Timing Diagram (Multiplexed) t13 ALE t11 t12 A[10:0] t14 R ...
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Table 11-9. SPI Interface Timing (VDD18 = 1.8V ±5%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, T (See Figure 11-11.) (Note 1) PARAMETER SCLK Frequency SCLK Cycle Time CS Setup to First SCLK Edge CS Hold Time After Last ...
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Figure 11-11. SPI Interface Timing Diagram CPHA = SUC CYC SCLK, CPOL=0 t CLKH t SCLK, CLKL CPOL SUI HDI SDI SDO CPHA = SUC CYC SCLK, CPOL=0 t CLKH ...
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Table 11-10. JTAG Interface Timing (VDD18 = 1.8V ±5%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, T (See Figure 11-12.) PARAMETER JTCLK Clock Period JTCLK Clock High/Low Time (Note 1) JTCLK to JTDI, JTMS Setup Time JTCLK to JTDI, ...
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PIN ASSIGNMENTS Table 12-1. Pin Assignments Sorted by Signal Name for DS32506/DS32508/DS32512 SIGNAL BALL A0 V5 A1/LB5[1] T8 A2/LB6[1] W5 A3/LB7[1] R9 A4/LB8[1] Y4 A5/LB9[1] P9 A6/LB10[1] AA3 A7/LB11[1] T9 A8/LB12[1] AB2 A9/ITRE R10 A10 W6 AIST E7 ALE ...
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SIGNAL BALL GPIOA3/LM3[1] J7 GPIOA4/LM4[1] N6 GPIOA5/LM5[1] F8 GPIOA6/LM6[1] U11 GPIOA7/LM7[1] F11 GPIOA8/LM8[1] U13 GPIOA9/LM9[1] F13 GPIOA10/LM10[1] Y14 GPIOA11/LM11[1] F15 GPIOA12/LM12[1] Y18 GPIOB1/LM1[0] G2 GPIOB2/LM2[0] M4 GPIOB3/LM3[0] G5 GPIOB4/LM4[0] T1 GPIOB5/LM5[0] E8 GPIOB6/LM6[0] Y10 GPIOB7/LM7[0] B10 GPIOB8/LM8[0] AB14 GPIOB9/LM9[0] A14 ...
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SIGNAL BALL JVDD8 W11 JVDD9 E16 JVDD10 W14 JVDD11 E18 JVDD12 V17 JVSS1 H4 JVSS2 M2 JVSS3 B2 JVSS4 T3 JVSS5 A9 JVSS6 AB6 JVSS7 C13 JVSS8 V11 JVSS9 C16 JVSS10 V14 JVSS11 D19 JVSS12 W17 LBS H8 MT0 L21 ...
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Figure 12-1. DS32512 Pin Assignment, Hardware and Microprocessor Interfaces Left Half JVDD3 TVDD3 RCLKI B HW JVSS3 RPD C RST TXP3 TXP3 D TXN3 TXN3 JTDI E JTRST RXN3 RXP3 F TAIS1 RMON3 TVSS3 G VDD18 ...
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Right Half TXN7 TXP7 GPIOB9 RXN9 TXN7 TXP7 RMON9 RXP9 TVSS7 JVSS7 RVSS9 TVDD9 TVDD7 JVDD7 TVSS9 TVDD9 TVDD7 TLBO7 RVDD9 TVSS9 TVSS7 GPIOA9 TVSS9 GPIOA11 TVDD9 TAIS9 TVDD11 TAIS11 RNEG9 TPOS9 TDM7 TCLK9 VSS VDD33 RCLK5 ...
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Figure 12-2. DS32512 Pin Assignment, Hardware Interface Only Left Half JVDD3 TVDD3 RCLKI B HW JVSS3 RPD C RST TXP3 TXP3 D TXN3 TXN3 JTDI E JTRST RXN3 RXP3 F TAIS1 RMON3 TVSS3 G VDD18 LM1[0] ...
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Right Half TXN7 TXP7 LM9[0] RXN9 TXN7 TXP7 RMON9 RXP9 TVSS7 JVSS7 RVSS9 TVDD9 TVDD7 JVDD7 TVSS9 TVDD9 TVDD7 TLBO7 RVDD9 TVSS9 TVSS7 LM9[1] TVSS9 LM11[1] TVDD9 TAIS9 TVDD11 TAIS11 RNEG9 TPOS9 TDM7 TCLK9 VSS VDD33 RCLK5 ...
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Figure 12-3. DS32512 Pin Assignment, Microprocessor Interface Only Left Half JVDD3 TVDD3 N. JVSS3 N.C. C RST TXP3 TXP3 D TXN3 TXN3 JTDI E JTRST RXN3 RXP3 F N.C. N.C. TVSS3 G VDD18 GPIOB1 ...
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Right Half TXN7 TXP7 GPIOB9 RXN9 TXN7 TXP7 N.C. RXP9 TVSS7 JVSS7 RVSS9 TVDD9 TVDD7 JVDD7 TVSS9 TVDD9 TVDD7 N.C. RVDD9 TVSS9 TVSS7 GPIOA9 TVSS9 GPIOA11 TVDD9 N.C. TVDD11 N.C. RNEG9 TPOS9 N.C. TCLK9 VSS VDD33 RCLK5 ...
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Figure 12-4. DS32508 Pin Assignment, Hardware and Microprocessor Interfaces Left Half JVDD3 TVDD3 RCLKI B HW JVSS3 RPD C RST TXP3 TXP3 D TXN3 TXN3 JTDI E JTRST RXN3 RXP3 F TAIS1 RMON3 TVSS3 G VDD18 ...
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Right Half TXN7 TXP7 N.C. N.C. TXN7 TXP7 N.C. N.C. TVSS7 JVSS7 VSS VSS TVDD7 JVDD7 VSS VSS TVDD7 TLBO7 VSS VSS TVSS7 N.C. VSS N.C. VSS N.C. VSS N.C. N.C. N.C. TDM7 N.C. VSS VDD33 RCLK5 ...
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Figure 12-5. DS32508 Pin Assignment, Hardware Interface Only Left Half JVDD3 TVDD3 RCLKI B HW JVSS3 RPD C RST TXP3 TXP3 D TXN3 TXN3 JTDI E JTRST RXN3 RXP3 F TAIS1 RMON3 TVSS3 G VDD18 LM1[0] ...
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Right Half TXN7 TXP7 N.C. N.C. TXN7 TXP7 N.C. N.C. TVSS7 JVSS7 VSS VSS TVDD7 JVDD7 VSS VSS TVDD7 TLBO7 VSS VSS TVSS7 N.C. VSS N.C. VSS N.C. VSS N.C. N.C. N.C. TDM7 N.C. VSS VDD33 RCLK5 ...
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Figure 12-6. DS32508 Pin Assignment, Microprocessor Interface Only Left Half JVDD3 TVDD3 N. JVSS3 N.C. C RST TXP3 TXP3 D TXN3 TXN3 JTDI E JTRST RXN3 RXP3 F N.C. N.C. TVSS3 G VDD18 GPIOB1 ...
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Right Half TXN7 TXP7 N.C. N.C. TXN7 TXP7 N.C. N.C. TVSS7 JVSS7 VSS VSS TVDD7 JVDD7 VSS VSS TVDD7 N.C. VSS VSS TVSS7 N.C. VSS N.C. VSS N.C. VSS N.C. N.C. N.C. N.C. N.C. VSS VDD33 RCLK5 ...
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Figure 12-7. DS32506 Pin Assignment, Hardware and Microprocessor Interfaces Left Half JVDD3 TVDD3 RCLKI B HW JVSS3 RPD C RST TXP3 TXP3 D TXN3 TXN3 JTDI E JTRST RXN3 RXP3 F TAIS1 RMON3 TVSS3 G VDD18 ...
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Right Half N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS VSS VSS VSS VSS VSS VSS VSS VSS N.C. VSS VSS VSS N.C. VSS N.C. VSS N.C. VSS N.C. N.C. N.C. N.C. N.C. VSS VDD33 RCLK5 ...
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Figure 12-8. DS32506 Pin Assignment, Hardware Interface Only Left Half JVDD3 TVDD3 RCLKI B HW JVSS3 RPD C TXP3 TXP3 RST D TXN3 TXN3 JTDI E JTRST RXN3 RXP3 F TAIS1 RMON3 TVSS3 G VDD18 LM1[0] ...
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Right Half N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS VSS VSS VSS VSS VSS VSS VSS VSS N.C. VSS VSS VSS N.C. VSS N.C. VSS N.C. VSS N.C. N.C. N.C. N.C. N.C. VSS VDD33 RCLK5 ...
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Figure 12-9. DS32506 Pin Assignment, Microprocessor Interface Only Left Half JVDD3 TVDD3 N. JVSS3 N.C. C RST TXP3 TXP3 D TXN3 TXN3 JTDI E JTRST RXN3 RXP3 F N.C. N.C. TVSS3 G VDD18 GPIOB1 ...
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Right Half N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS VSS VSS VSS VSS VSS VSS VSS VSS N.C. VSS VSS VSS N.C. VSS N.C. VSS N.C. VSS N.C. N.C. N.C. N.C. N.C. VSS VDD33 RCLK5 ...
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PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 13.1 484-Lead BGA (23mm x 23mm) (56-G60038-001) ...
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THERMAL INFORMATION Table 14-1. Thermal Properties, Natural Convection PARAMETER Ambient Temperature (Note 1) Junction Temperature Theta - JA ( θ ), Still Air (Note 1) JA Theta-JC ( θ Psi-JB Psi-JT Note 1: The package is mounted ...
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ACRONYMS AND ABBREVIATIONS AIS Alarm Indication Signal AMI Alternate Mark Inversion B3ZS Bipolar with Three-Zero Substitution BER Bit-Error Rate, Bit-Error Ratio BPV Bipolar Violation CV Code Violation DS3 Digital Signal, Level 3 EXZ Excessive Zeros HDB3 High-Density Bipolar of ...
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