DS2155LC2 Maxim Integrated, DS2155LC2 Datasheet
DS2155LC2
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DS2155LC2 Summary of contents
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GENERAL DESCRIPTION The DS2155 is a software-selectable T1, E1 single-chip transceiver (SCT) for short-haul and long-haul applications. The DS2155 is composed of a line interface unit (LIU), framer, HDLC controllers, and a TDM backplane interface, and is ...
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TABLE OF CONTENTS 1. TABLE OF CONTENTS ............................................................................................................................2 1 ........................................................................................................................................6 ABLE OF IGURES 1 ..........................................................................................................................................7 ABLE OF ABLES 2. DATA SHEET REVISION HISTORY .....................................................................................................8 3. MAIN FEATURES....................................................................................................................................10 3 UNCTIONAL ESCRIPTION 3 ...
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I/O PIN CONFIGURATION OPTIONS.................................................................................................69 13. LOOPBACK CONFIGURATION ..........................................................................................................71 13 HANNEL OOPBACK 14. ERROR COUNT REGISTERS ...............................................................................................................75 14 INE ODE IOLATION 14.1.1 T1 Operation.......................................................................................................................................76 14.1.2 E1 Operation.......................................................................................................................................76 14 ATH ODE ...
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ETHOD ARDWARE 22 ETHOD NTERNAL 22 ETHOD NTERNAL 23. HDLC CONTROLLERS ........................................................................................................................126 23 ASIC PERATION ETAILS 23.2 HDLC C ONFIGURATION 23.2.1 FIFO Control....................................................................................................................................130 23.3 HDLC M ....................................................................................................................................131 ...
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C I HANNEL NTERLEAVE 28 ..............................................................................................................................184 RAME NTERLEAVE 29. EXTENDED SYSTEM INFORMATION BUS (ESIB) .......................................................................187 30. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER ........................................................191 31. FRACTIONAL T1/E1 SUPPORT .........................................................................................................191 32. USER-PROGRAMMABLE OUTPUT PINS........................................................................................193 33. TRANSMIT FLOW DIAGRAMS .........................................................................................................194 34. JTAG ...
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Table of Figures Figure 3-1. Block Diagram ........................................................................................................................................ 15 Figure 3-2. Receive and Transmit LIU...................................................................................................................... 16 Figure 3-3. Receive and Transmit Framer/HDLC ..................................................................................................... 17 Figure 3-4. Backplane Interface ................................................................................................................................ 18 Figure 4-1. 10mm CSBGA Pin Configuration .......................................................................................................... 32 Figure ...
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Figure 35-23. Transmit IBO Frame Interleave Mode Timing ................................................................................. 221 Figure 37-1. Intel Multiplexed Bus Read Timing (BTS = 0/MUX = 1).................................................................. 225 Figure 37-2. Intel Multiplexed Bus Write Timing (BTS = 0/MUX = 1)................................................................. 225 Figure 37-3. Motorola Multiplexed ...
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DATA SHEET REVISION HISTORY REVISION In Section 3: Line Interface and Section 3.1: Functional Description, corrected dB values for E1 and T1 (page 10 and page 13): 080607 E1 -43dB and 0 to -12dB T1 ...
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REVISION The definition of the EGL bit in the LIC1 register has been corrected for both T1 and E1 mode. T1 Mode: EGL = 1 was changed from 15dB to –15dB E1 Mode: EGL = 0 was changed from –10dB ...
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MAIN FEATURES The DS2155 contains all of the features of the previous generation of Dallas Semiconductor’s T1 and E1 SCTs plus many new features. General Programmable output clocks for fractional T1, E1, H0, and H12 applications Interleaving PCM bus ...
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Flexible signaling support – Software or hardware based – Interrupt generated on change of signaling data – Receive signaling freeze on loss-of-sync, carrier loss, or frame slip Addition of hardware pins to indicate carrier loss and signaling freeze Automatic RAI ...
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The DS2155 is compliant with the following standards: ANSI: T1.403-1995, T1.231–1993, T1.408 AT&T: TR54016, TR62411 ITU: G.703, G.704, G.706, G.736, G.775, G.823, G.932, I.431, O.151, Q.161 ITU-T: Recommendation I.432–03/93 B-ISDN User-Network Interface—Physical Layer Specification ETSI: ETS 300 011, ETS 300 ...
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Functional Description The DS2155 is a software-selectable T1, E1 single-chip transceiver (SCT) for short-haul and long- haul applications. The DS2155 is composed of an LIU, framer, HDLC controllers, and a TDM backplane interface, and is controlled by ...
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Reader’s Note: This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125µs frame there are 24 8-bit channels plus a framing bit assumed that the framing bit is sent first followed by channel ...
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Block Diagram Figure 3-1 shows a simplified block diagram featuring the major components of the DS2155. Details are shown in subsequent figures. The block diagram is divided into three functional blocks: LIU, FRAMER, and BACKPLANE INTERFACE. Figure 3-1. Block ...
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Figure 3-2. Receive and Transmit LIU 32.768MHz RRING RTIP TRING TTIP VCO / PLL MUX 16 of 238 RCL MUX JACLK RPOS RNEG RCLK TPOS TNEG TCLK ...
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Figure 3-3. Receive and Transmit Framer/HDLC RPOS RNEG RCLK TPOS TNEG TCLK REC HDLC #1 128 Byte FIFO MAPPER DATA RECEIVE CLOCK FRAMER SYNC SYNC TRANSMIT CLOCK FRAMER DATA MAPPER XMIT HDLC #1 128 Byte FIFO 17 of 238 REC ...
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Figure 3-4. Backplane Interface DATA CLOCK SYNC SYNC Sa/FDL DATA INSERT CLOCK JACLK Sa BIT/FDL EXTRACTION SIGNALING BUFFER ELASTIC STORE CHANNEL TIMING SIGNALING BUFFER ELASTIC STORE CHANNEL TIMING TCLK MUX 18 of 238 RLINK RLCLK RSIG RSIGFR RSYSCLK RSER RCLK ...
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PIN FUNCTION DESCRIPTION 4.1 Transmit Side Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 1.544MHz (T1 2.048MHz (E1) primary clock. Used to clock data through the transmit-side formatter. TCLK can be internally sourced from ...
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Signal Name: TLINK Signal Description: Transmit Link Data Signal Type: Input If enabled, this pin is sampled on the falling edge of TCLK for data insertion into either the FDL stream (ESF) or the Fs-bit position (D4), or the Z-bit ...
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Signal Description: Transmit Clock Output Signal Type: Output Buffered clock that is used to clock data through the transmit-side formatter (i.e., either TCLK or RCLKI). This pin is normally connected to TCLKI. Signal Name: TPOSI Signal Description: Transmit Positive-Data Input ...
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Signal Name: RCHBLK Signal Description: Receive Channel Block Signal Type: Output A user-programmable output that can be forced high or low during any of the channels. Synchronous with RCLK when the receive-side elastic store is ...
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Signal Name: RLOS/LOTC Signal Description: Receive Loss-of-Sync/Loss-of-Transmit Clock Signal Type: Output A dual function output that is controlled by the CCR1.0 control bit. This pin can be programmed to either toggle high when the synchronizer is searching for the frame ...
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Signal Name: RCLKI Signal Description: Receive Clock Input Signal Type: Input Clock used to clock data through the receive-side framer. This pin is normally connected to RCLKO. Can be internally connected to RCLKO by connecting the LIUC pin high. 4.3 ...
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Signal Name: CS Signal Description: Chip Select Signal Type: Input Must be low to read or write to the device active-low signal. Signal Name: ALE(AS)/A7 Signal Description: Address Latch Enable (Address Strobe Signal Type: Input ...
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User Output Port Pins Signal Name: UOP0 Signal Description: User Output Port 0 Signal Type: Output This output port pin can be set low or high by the CCR4.0 control bit. This pin is forced low on power-up and ...
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JTAG Test Access Port Pins Signal Name: JTRST Signal Description: IEEE 1149.1 Test Reset Signal Type: Input JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from low to high. This ...
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Line Interface Pins Signal Name: MCLK Signal Description: Master Clock Input Signal Type: Input A (50ppm) clock source is applied at this pin. This clock is used internally for both clock/data recovery and for the jitter attenuator for T1 ...
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Supply Pins Signal Name: DVDD Signal Description: Digital Positive Supply Signal Type: Supply 3.3V ±5%. Should be connected to the RVDD and TVDD pins. Signal Name: RVDD Signal Description: Receive Analog Positive Supply Signal Type: Supply 3.3V ±5%. Should ...
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L and G Package Pinout The DS2155 is available in either a 100-pin LQFP (L) or 10mm CSBGA, 0.8mm pitch (G) package. Table 4-A. Pin Description Sorted by Pin Number PIN LQFP CSBGA ...
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PIN LQFP CSBGA 51 K10 J10 H10 F10 E10 D10 ...
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CSBGA Pin Configuration Figure 4-1. 10mm CSBGA Pin Configuration RLOS/ RCHBLK RFSYNC LOTC B JTCLK JTMS RSYSCLK C JTDI RCL BPCLK D JTDO UOP1 UOP0 E 8XCLK LIUC BTS F RTIP RRING RVDD G ...
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PARALLEL PORT The SCT is controlled by either a nonmultiplexed (MUX = multiplexed (MUX = 1) bus through an external microcontroller or microprocessor. The SCT can operate with either Intel or Motorola bus timing configurations. If ...
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ADDRESS R/W xxh 25 R/W Interrupt Mask Register 8 26 R/W Status Register 9 27 R/W Interrupt Mask Register 9 28 R/W Per-Channel Pointer Register 29 W Per-Channel Data Register Per-Channel Data Register Per-Channel ...
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ADDRESS R/W xxh 54 R/W Transmit Signaling Register 5 55 R/W Transmit Signaling Register 6 56 R/W Transmit Signaling Register 7 57 R/W Transmit Signaling Register 8 58 R/W Transmit Signaling Register 9 59 R/W Transmit Signaling Register 10 5A ...
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ADDRESS R/W xxh 83 R/W Transmit Idle Code Enable Register 4 84 R/W Receive Idle Code Enable Register 1 85 R/W Receive Idle Code Enable Register 2 86 R/W Receive Idle Code Enable Register 3 87 R/W Receive Idle Code ...
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ADDRESS R/W xxh B2 R Extend System Information Bus Register Extend System Information Bus Register Extend System Information Bus Register Extend System Information Bus Register 4 B6 R/W In-Band Code Control ...
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ADDRESS R/W xxh E1 R/W BERT Control Register 2 E2 — Unused E3 R BERT Bit Count Register BERT Bit Count Register BERT Bit Count Register BERT Bit Count Register 4 ...
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PROGRAMMING MODEL The DS2155 register map is divided into three groups: T1 specific features, E1 specific features, and common features. The typical programming sequence begins with issuing a reset to the DS2155, selecting operation in the ...
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Power-Up Sequence The DS2155 contains an on-chip power-up reset function that automatically clears the writeable register space immediately after power is supplied to the DS2155. The user can issue a chip reset at any time. Issuing a reset disrupts ...
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Interrupt Handling Various alarms, conditions, and events in the DS2155 can cause interrupts. For simplicity, these are all referred to as events in this explanation. All status registers can be programmed to produce interrupts. Each status register has an ...
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Information Registers Information registers operate the same as status registers except they cannot cause interrupts. They are all latched except for INFO7 and some of the bits in INFO5 and INFO6. INFO7 register is a read-only register. It reports ...
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SPECIAL PER-CHANNEL REGISTER OPERATION Some of the features described in the data sheet that operate on a per-channel basis use a special method for channel selection. There are five registers involved: per-channel pointer register (PCPR) and per- channel data ...
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Register Name: PCDR1 Register Description: Per-Channel Data Register 1 Register Address: 29h Bit # 7 6 Name — — Default CH8 CH7 Register Name: PCDR2 Register Description: Per-Channel Data Register 2 Register Address: 2Ah Bit # 7 6 Name — ...
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CLOCK MAP Figure 8-1 shows the clock map of the DS2155. The routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuator, which can ...
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T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS The T1 framer portion of the DS2155 is configured through a set of nine control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS2155 ...
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Register Name: T1RCR2 Register Description: T1 Receive Control Register 2 Register Address: 04h Bit # 7 6 Name — RFM Default 0 0 Bit 0/Receive-Side D4 Yellow Alarm Select (RD4YM bit 2 of all channels 1 ...
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Register Name: T1TCR1 Register Description: T1 Transmit Control Register 1 Register Address: 05h Bit # 7 6 Name TJC TFPT Default 0 0 Bit 0/Transmit Yellow Alarm (TYEL not transmit yellow alarm 1 = transmit yellow alarm ...
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Register Name: T1TCR2 Register Description: T1 Transmit Control Register 2 Register Address: 06h Bit # 7 6 Name TB8ZS TSLC96 Default 0 0 Bit 0/Transmit-Side Bit 7 Zero-Suppression Enable (TB7ZS stuffing occurs 1 = bit 7 forced ...
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Register Name: T1CCR1 Register Description: T1 Common Control Register 1 Register Address: 07h Bit # 7 6 Name — — Default 0 0 Bit 0/Transmit Loop-Code Enable (TLOOP). See Section 0 = transmit data normally 1 = replace normal transmitted ...
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T1 Transmit Transparency The software signaling insertion-enable registers, SSIE1–SSIE4, can be used to select signaling insertion from the transmit signaling registers, TS1–TS12 per-channel basis. Setting a bit in the SSIEx register allows signaling data to be sourced ...
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T1 Receive-Side Digital-Milliwatt Code Generation Receive-side digital-milliwatt code generation involves using the receive digital-milliwatt registers (T1RDMR1/2/3) to determine which of the 24 T1 channels of the T1 line going to the backplane should be overwritten with a digital-milliwatt pattern. ...
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Register Name: INFO1 Register Description: Information Register 1 Register Address: 10h Bit # 7 6 Name RPDV TPDV Default 0 0 Bit 0/Frame Bit-Error Event (FBE). Set when an Ft (D4) or FPS (ESF) framing bit is received in error. ...
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Table 9-A. T1 Alarm Criteria ALARM Blue Alarm (AIS) (Note 1) Yellow Alarm (RAI) D4 Bit 2 Mode (T1RCR2 12th F-Bit Mode (T1RCR2 this mode is also referred to as the “Japanese Yellow Alarm”) ESF ...
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E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS The E1 framer portion of the DS2155 is configured by a set of four control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS2155 ...
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Table 10-A. E1 Sync/Resync Criteria FRAME OR MULTIFRAME SYNC CRITERIA LEVEL FAS present in frame N and FAS FAS not present in frame Two valid MF alignment CRC4 words found within 8ms Valid MF ...
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Register Name: E1TCR1 Register Description: E1 Transmit Control Register 1 Register Address: 35h Bit # 7 6 Name TFPT T16S Default 0 0 Bit 0/Transmit CRC4 Enable (TCRC4 CRC4 disabled 1 = CRC4 enabled Bit 1/Transmit G.802 Enable ...
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Register Name: E1TCR2 Register Description: E1 Transmit Control Register 2 Register Address: 36h Bit # 7 6 Name Sa8S Sa7S Default 0 0 Bit 0/Automatic Remote Alarm Generation (ARA disabled 1 = enabled Bit 1/Automatic AIS Generation (AAIS) ...
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Automatic Alarm Generation The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is enabled (E1TCR2.1 = 1), the device monitors the receive-side framer to determine if any of the following conditions are ...
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E1 Information Registers Register Name: INFO3 Register Description: Information Register 3 Register Address: 12h Bit # 7 6 Name — — Default 0 0 Bit 0/CAS Resync Criteria Met Event (CASRC). Set when two consecutive CAS MF alignment words ...
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Table 10-B. E1 Alarm Criteria ALARM SET CRITERIA An RLOS condition exists on power-up prior to initial synchronization, when a RLOS resync criteria has been met, or when a manual resync has been initiated by E1RCR1.0 RCL 255 or 2048 ...
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COMMON CONTROL AND STATUS REGISTERS Register Name: CCR1 Register Description: Common Control Register 1 Register Address: 70h Bit # 7 6 Name MCLKS CRC4R Default 0 0 Bit 0/Function of the RLOS/LOTC Output (RLOSF receive loss of ...
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Register Name: IDR Register Description: Device Identification Register Register Address: 0Fh Bit # 7 6 Name ID7 ID6 Default 1 0 Bits 0 to 3/Chip Revision Bits (ID0 to ID3). The lower four bits of the IDR are used to ...
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Register Name: IMR2 Register Description: Interrupt Mask Register 2 Register Address: 19h Bit # 7 6 Name RYELC RUA1C Default 0 0 Bit 0/Receive Loss-of-Sync Condition (RLOS interrupt masked 1 = interrupt enabled—interrupts on rising edge only Bit ...
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Register Name: SR3 Register Description: Status Register 3 Register Address: 1Ah Bit # 7 6 Name LSPARE LDN Default 0 0 Bit 0/Receive Remote Alarm Condition (RRA) (E1 Only). Set when a remote alarm is received at RPOSI and RNEGI. ...
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Register Name: IMR3 Register Description: Interrupt Mask Register 3 Register Address: 1Bh Bit # 7 6 Name LSPARE LDN Default 0 0 Bit 0/Receive Remote Alarm Condition (RRA interrupt masked 1 = interrupt enabled—interrupts on rising and falling ...
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Register Name: SR4 Register Description: Status Register 4 Register Address: 1Ch Bit # 7 6 Name RAIS-CI RSAO Default 0 0 Bit 0/Receive Align Frame Event (RAF) (E1 Only). Set every 250µs at the beginning of align frames. Used to ...
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Register Name: IMR4 Register Description: Interrupt Mask Register 4 Register Address: 1Dh Bit # 7 6 Name RAIS-CI RSAO Default 0 0 Bit 0/Receive Align Frame Event (RAF interrupt masked 1 = interrupt enabled Bit 1/Receive CRC4 Multiframe ...
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I/O PIN CONFIGURATION OPTIONS Register Name: IOCR1 Register Description: I/O Configuration Register 1 Register Address: 01h Bit # 7 6 Name RSMS RSMS2 Default 0 0 Bit 0/Output Data Format (ODF bipolar data at TPOSO and TNEGO ...
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Register Name: IOCR2 Register Description: I/O Configuration Register 2 Register Address: 02h Bit # 7 6 Name RCLKINV TCLKINV Default 0 0 Bit 0/RSYSCLK Mode Select (RSCLKM RSYSCLK is 1.544MHz RSYSCLK is 2.048MHz or ...
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LOOPBACK CONFIGURATION Register Name: LBCR Register Description: Loopback Control Register Register Address: 4Ah Bit # 7 6 Name — — Default 0 0 Bit 0/Framer Loopback (FLB). This loopback is useful in testing and debugging applications. In FLB, the ...
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Bit 3/Local Loopback (LLB). In this loopback, data continues to be transmitted as normal through the transmit side of the SCT. Data being received at RTIP and RRING are replaced with the data being transmitted. Data in this loopback passes ...
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Per-Channel Loopback The per-channel loopback registers (PCLRs) determine which channels (if any) from the backplane should be replaced with the data from the receive side or, i.e., off of the line. If this loopback is enabled, ...
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Register Name: PCLR3 Register Description: Per-Channel Loopback Enable Register 3 Register Address: 4Dh Bit # 7 6 Name CH24 CH23 Default 0 0 Bits 0 to 7/Per-Channel Loopback Enable for Channels (CH17 to CH24 loopback ...
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ERROR COUNT REGISTERS The DS2155 contains four counters that are used to accumulate line-coding errors, path errors, and synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62ms (E1 mode only), or manual. See Error-Counter Configuration ...
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Line-Code Violation Count Register (LCVCR) 14.1.1 T1 Operation T1 code violations are defined as bipolar violations (BPVs) or excessive 0s. If the B8ZS mode is set for the receive side, then B8ZS codewords are not counted. This counter is ...
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Register Name: LCVCR1 Register Description: Line-Code Violation Count Register 1 Register Address: 42h Bit # 7 6 Name LCVC15 LCVC14 Default 0 0 Bits 0 to 7/Line-Code Violation Counter Bits (LCVC8 to LCVC15). LCV15 is the MSB ...
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Path Code Violation Count Register (PCVCR) 14.2.1 T1 Operation The path code violation count register records Ft, Fs, or CRC6 errors in T1 frames. When the receive side of a framer is set to operate in the T1 ESF ...
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Frames Out-of-Sync Count Register (FOSCR) 14.3.1 T1 Operation The FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync. This number is useful in ESF applications needing to measure the parameters loss-of-frame ...
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E-Bit Counter (EBCR) This counter is only available in E1 mode. E-bit count register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a 16-bit counter that records far-end block errors (FEBE) as ...
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DS0 MONITORING FUNCTION The DS2155 has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel ...
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Register Name: RDS0SEL Register Description: Receive Channel Monitor Select Register Address: 76h Bit # 7 6 Name — — Default 0 0 Bits 0 to 4/Receive Channel Monitor Bits (RCM0 to RCM4). RCM0 is the LSB of a 5-bit channel ...
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SIGNALING OPERATION There are two methods to access receive signaling data and provide transmit signaling data, processor- based (software-based) or hardware-based. Processor-based refers to access through the transmit and receive signaling registers RS1–RS16 and TS1–TS16. Hardware-based refers to the ...
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Hardware-Based Receive Signaling In hardware-based signaling the signaling data can be obtained from the RSER pin or the RSIG pin. RSIG is a signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The signaling data, T1 ...
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Register Name: SIGCR Register Description: Signaling Control Register Register Address: 40h Bit # 7 6 Name GRSRE — Default 0 0 Bit 0/Force Receive Signaling All Ones (FRSAO mode, this bit forces all signaling data at the RSIG ...
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Register Name: RS1 to RS12 Register Description: Receive Signaling Registers (T1 Mode, ESF Format) Register Address: 60h to 6Bh (MSB) CH2-A CH2-B CH2-C CH4-A CH4-B CH4-C CH6-A CH6-B CH6-C CH8-A CH8-B CH8-C CH10-A CH10-B CH10-C CH12-A CH12-B CH12-C CH14-A CH14-B ...
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Register Name: RS1 to RS16 Register Description: Receive Signaling Registers (E1 Mode, CAS Format) Register Address: 60h to 6Fh (MSB CH2-A CH2-B CH2-C CH4-A CH4-B CH4-C CH6-A CH6-B CH6-C CH8-A CH8-B CH8-C CH10-A CH10-B CH10-C CH12-A CH12-B ...
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Register Name: RSCSE1, RSCSE2, RSCSE3, RSCSE4 Register Description: Receive Signaling Change-of-State Interrupt Enable Register Address: 3Ch, 3Dh, 3Eh, 3Fh (MSB) CH8 CH7 CH6 CH16 CH15 CH14 CH24 CH23 CH22 CH30 Setting any of the CH1–CH30 bits in the RSCSE1–RSCSE4 registers ...
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Transmit Signaling Figure 16-2. Simplified Diagram of Transmit Signaling Path T1/E1 DATA STREAM ONLY APPLIES TO T1 MODE 16.2.1 Processor-Based Mode In processor-based mode, signaling data is loaded into the transmit signaling registers (TS1–TS16) by the host interface. On ...
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E1 Mode In E1 mode, TS16 carries the signaling information. This information can be in either CCS (common channel signaling) or CAS (channel associated signaling) format. The 32 time slots are referenced by two different channel number schemes in ...
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Register Name: TS1 to TS16 Register Description: Transmit Signaling Registers (E1 Mode, CAS Format) Register Address: 50h to 5Fh (MSB CH2-A CH2-B CH2-C CH4-A CH4-B CH4-C CH6-A CH6-B CH6-C CH8-A CH8-B CH8-C CH10-A CH10-B CH10-C CH12-A CH12-B ...
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Register Name: TS1 to TS12 Register Description: Transmit Signaling Registers (T1 Mode, ESF Format) Register Address: 50h to 5Bh (MSB) CH2-A CH2-B CH2-C CH4-A CH4-B CH4-C CH6-A CH6-B CH6-C CH8-A CH8-B CH8-C CH10-A CH10-B CH10-C CH12-A CH12-B CH12-C CH14-A CH14-B ...
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Software Signaling Insertion-Enable Registers, E1 CAS Mode In E1 CAS mode, the CAS signaling alignment/alarm byte can be sourced from the transmit signaling registers along with the signaling data. Register Name: SSIE1 Register Description: Software Signaling Insertion Enable 1 ...
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Register Name: SSIE3 Register Description: Software Signaling Insertion Enable 3 Register Address: 0Ah Bit # 7 6 Name CH22 CH21 Default 0 0 Bit 0/Lower CAS Align/Alarm Word (LCAW). Selects the lower CAS align/alarm bits (xyxx sourced from ...
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Software Signaling Insertion-Enable Registers, T1 Mode In T1 mode, only registers SSIE1–SSIE3 are used since there are only 24 channels frame. Register Name: SSIE1 Register Description: Software Signaling Insertion Enable 1 Register Address: 08h Bit # ...
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PER-CHANNEL IDLE CODE GENERATION Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. When operated in the T1 mode, only the first 24 channels are used by the DS2155, ...
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Idle-Code Programming Examples Example 1 Sets transmit channel 3 idle code to 7Eh. Write IAAR = 02h ;select channel 3 in the array Write PCICR = 7Eh ;set idle code to 7Eh Example 2 Sets transmit channels 3, 4, ...
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Register Name: IAAR Register Description: Idle Array Address Register Register Address: 7Eh Bit # 7 6 Name GRIC GTIC Default 0 0 Bits 0 to 5/Channel Pointer Address Bits (IAA0 to IAA5). These bits select the channel to be programmed ...
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The transmit-channel idle-code enable registers (TCICE1/2/3/4) are used to determine which of the channels from the backplane to the line should be overwritten with the code placed in the per-channel code array. ...
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The receive-channel idle-code enable registers (RCICE1/2/3/4) are used to determine which of the channels from the backplane to the line should be overwritten with the code placed in the per-channel code array. ...
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CHANNEL BLOCKING REGISTERS The receive channel blocking registers (RCBR1/RCBR2/RCBR3/RCBR4) and the transmit channel blocking registers (TCBR1/TCBR2/TCBR3/TCBR4) control RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either high or low during ...
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Register Name: RCBR3 Register Description: Receive Channel Blocking Register 3 Register Address: 8Ah Bit # 7 6 Name CH24 CH23 Default 0 0 Bits 0 to 7/Receive Channels Channel Blocking Control Bits (CH17 to CH24 ...
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Register Name: TCBR1 Register Description: Transmit Channel Blocking Register 1 Register Address: 8Ch Bit # 7 6 Name CH8 CH7 Default 0 0 Bits 0 to 7/Transmit Channels Channel Blocking Control Bits (CH1 to CH8 ...
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ELASTIC STORES OPERATION The DS2155 contains dual two-frame elastic stores, one for the receive direction and one for the transmit direction. Both elastic stores are fully independent. The transmit and receive-side elastic stores can be enabled/disabled independently of each ...
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Register Name: ESCR Register Description: Elastic Store Control Register Register Address: 4Fh Bit # 7 6 Name TESALGN TESR Default 0 0 Bit 0/Receive Elastic Store Enable (RESE elastic store is bypassed 1 = elastic store is enabled ...
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Register Name: SR5 Register Description: Status Register 5 Register Address: 1Eh Bit # 7 6 Name — — Default 0 0 Bit 0/Receive Elastic Store Slip-Occurrence Event (RSLIP). Set when the receive elastic store has either repeated or deleted a ...
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Receive Side See the IOCR1 and IOCR2 registers for information about clock and I/O configurations. If the receive-side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the RSYSCLK pin. For higher ...
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T1 Mode If the user selects to apply a 2.048MHz clock to the TSYSCLK pin, then the data input at TSER is ignored every fourth channel. Therefore channels 13, 17, 21, 25, and 29 (time slots ...
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G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY) The DS2155 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSER already has the FAS/NFAS, CRC multiframe alignment word, and ...
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T1 BIT-ORIENTED CODE (BOC) CONTROLLER The DS2155 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. 21.1 Transmit BOC Bits ...
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Register Name: BOCC Register Description: BOC Control Register Register Address: 37h Bit # 7 6 Name — — Default 0 0 Bit 0/Send BOC (SBOC). Set = 1 to transmit the BOC code placed in bits ...
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Register Name: SR8 Register Description: Status Register 8 Register Address: 24h Bit # 7 6 Name — — Default 0 0 Bit 0/Receive BOC Detector Change-of-State Event (RBOC). Set whenever the BOC detector sees a change of state to a ...
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ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY) When operated in the E1 mode, the DS2155 provides three methods for accessing the Sa and the Si bits. The first method involves a hardware scheme that uses the RLINK/RLCLK ...
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Register Name: RAF Register Description: Receive Align Frame Register Register Address: C6h Bit # 7 6 Name Si 0 Default 0 0 Bit 0/Frame Alignment Signal Bit (1) Bit 1/Frame Alignment Signal Bit (1) Bit 2/Frame Alignment Signal Bit (0) ...
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Register Name: TAF Register Description: Transmit Align Frame Register Register Address: D0h Bit # 7 6 Name Si 0 Default 0 0 Bit 0/Frame Alignment Signal Bit (1) Bit 1/Frame Alignment Signal Bit (1) Bit 2/Frame Alignment Signal Bit (0) ...
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Method 3: Internal Register Scheme Based on CRC4 Multiframe The receive side contains a set of eight registers (RSiAF, RSiNAF, RRA, and RSa4–RSa8) that report the Si and Sa bits as they are received. These registers are updated with ...
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Register Name: RSiNAF Register Description: Received Si Bits of the Nonalign Frame Register Address: C9h Bit # 7 6 Name SiF1 SiF3 Default 0 0 Bit 0/Si Bit of Frame 15 (SiF15) Bit 1/Si Bit of Frame 13 (SiF13) Bit ...
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Register Name: RSa4 Register Description: Received Sa4 Bits Register Address: CBh Bit # 7 6 Name RSa4F1 RSa4F3 Default 0 0 Bit 0/Sa4 Bit of Frame 15 (RSa4F15) Bit 1/Sa4 Bit of Frame 13 (RSa4F13) Bit 2/Sa4 Bit of Frame ...
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Register Name: RSa6 Register Description: Received Sa6 Bits Register Address: CDh Bit # 7 6 Name RSa6F1 RSa6F3 Default 0 0 Bit 0/Sa6 Bit of Frame 15 (RSa6F15) Bit 1/Sa6 Bit of Frame 13 (RSa6F13) Bit 2/Sa6 Bit of Frame ...
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Register Name: RSa8 Register Description: Received Sa8 Bits Register Address: CFh Bit # 7 6 Name RSa8F1 RSa8F3 Default 0 0 Bit 0/Sa8 Bit of Frame 15 (RSa8F15) Bit 1/Sa8 Bit of Frame 13 (RSa8F13) Bit 2/Sa8 Bit of Frame ...
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Register Name: TSiNAF Register Description: Transmit Si Bits of the Nonalign Frame Register Address: D3h Bit # 7 6 Name TSiF1 TSiF3 Default 0 0 Bit 0/Si Bit of Frame 15 (TSiF15) Bit 1/Si Bit of Frame 13 (TSiF13) Bit ...
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Register Name: TSa4 Register Description: Transmit Sa4 Bits Register Address: D5h Bit # 7 6 Name TSa4F1 TSa4F3 Default 0 0 Bit 0/Sa4 Bit of Frame 15 (TSa4F15) Bit 1/Sa4 Bit of Frame 13 (TSa4F13) Bit 2/Sa4 Bit of Frame ...
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Register Name: TSa6 Register Description: Transmit Sa6 Bits Register Address: D7h Bit # 7 6 Name TSa6F1 TSa6F3 Default 0 0 Bit 0/Sa6 Bit of Frame 15 (TSa6F15) Bit 1/Sa6 Bit of Frame 13 (TSa6F13) Bit 2/Sa6 Bit of Frame ...
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Register Name: TSa8 Register Description: Transmit Sa8 Bits Register Address: D9h Bit # 7 6 Name TSa8F1 TSa8F3 Default 0 0 Bit 0/Sa8 Bit of Frame 15 (TSa8F15) Bit 1/Sa8 Bit of Frame 13 (TSa8F13) Bit 2/Sa8 Bit of Frame ...
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Register Name: TSACR Register Description: Transmit Sa Bit Control Register Register Address: DAh Bit # 7 6 Name SiAF SiNAF Default 0 0 Bit 0/Additional Bit 8 Insertion Control Bit (Sa8 not insert data from the TSa8 ...
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HDLC CONTROLLERS This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is configurable for use with time slots, Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). Each HDLC controller has 128-byte ...
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Table 23-A. HDLC Controller Registers REGISTER CONTROL AND CONFIGURATION H1TC, HDLC #1 Transmit Control Register H2TC, HDLC #2 Transmit Control Register H1RC, HDLC #1 Receive Control Register H2RC, HDLC #2 Receive Control Register H1FC, HDLC #1 FIFO Control Register H2FC, ...
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Register Name: H1TC, H2TC Register Description: HDLC #1 Transmit Control HDLC #2 Transmit Control Register Address: 90h, A0h Bit # 7 6 Name NOFS TEOML Default 0 0 Bit 0/Transmit CRC Defeat (TCRCD). A 2-byte CRC code is automatically appended ...
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Register Name: H1RC, H2RC Register Description: HDLC #1 Receive Control HDLC #2 Receive Control Register Address: 31h, 32h Bit # 7 6 Name RHR RHMS Default 0 0 Bit 0/Receive SS7 Fill-In Signal Unit Delete (RSFD normal operation; ...
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FIFO Control The FIFO control register (HxFC) controls and sets the watermarks for the transmit and receive FIFOs. Bits 3, 4, and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark. When ...
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HDLC Mapping 23.3.1 Receive The HDLC controllers must be assigned a space in the T1/E1 bandwidth in which they transmit and receive data. The controllers can be mapped to either the FDL (T1), Sa bits (E1 channels. ...
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Register Name: H1RTSBS, H2RTSBS Register Description: HDLC # 1 Receive Time Slot Bits/Sa Bits Select HDLC # 2 Receive Time Slot Bits/Sa Bits Select Register Address: 96h, A6h Bit # 7 6 Name RCB8SE RCB7SE Default 0 0 Bit 0/Receive ...
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Transmit The HxTCS1–HxTCS4 registers are used to assign the transmit controllers to channels 1–24 (T1) or 1–32 (E1) according to the following table. Register Channels HxTCS1 1–8 HxTCS2 9–16 HxTCS3 17–24 HxTCS4 25–32 Register Name: H1TCS1, H1TCS2, H1TCS3, H1TCS4 ...
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Register Name: H1TTSBS, H2TTSBS Register Description: HDLC # 1 Transmit Time Slot Bits/Sa Bits Select HDLC # 2 Transmit Time Slot Bits/Sa Bits Select Register Address: 9Bh, ABh Bit # 7 6 Name TCB8SE TCB7SE Default 0 0 Bit 0/Transmit ...
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Register Name: SR6, SR7 Register Description: HDLC #1 Status Register 6 HDLC #2 Status Register 7 Register Address: 20h, 22h Bit # 7 6 Name — TMEND Default 0 0 Bit 0/Transmit FIFO Not Full Condition (TNF). Set when the ...
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Register Name: IMR6, IMR7 Register Description: HDLC # 1 Interrupt Mask Register 6 HDLC # 2 Interrupt Mask Register 7 Register Address: 21h, 23h Bit # 7 6 Name — TMEND Default 0 0 Bit 0/Transmit FIFO Not Full Condition ...
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Register Name: INFO5, INFO6 Register Description: HDLC #1 Information Register HDLC #2 Information Register Register Address: 2Eh, 2Fh Bit # 7 6 Name — — Default 0 0 Bits 0 to 2/Receive Packet Status (PS0 to PS2). These are real-time ...
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FIFO Information The transmit FIFO buffer-available register indicates the number of bytes that can be written into the transmit FIFO. The count form this register informs the host as to how many bytes can be written into the transmit ...
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HDLC FIFOs Register Name: H1TF, H2TF Register Description: HDLC # 1 Transmit FIFO HDLC # 2 Transmit FIFO Register Address: 9Dh, ADh Bit # 7 6 Name THD7 THD6 Default 0 0 Bit 0/Transmit HDLC Data Bit 0 (THD0). ...
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Receive HDLC Code Example The following is an example of a receive HDLC routine: Reset receive HDLC controller. 1) Set HDLC mode, mapping, and high watermark. 2) Start new message buffer. 3) Enable RPE and RHWM interrupts. 4) Wait ...
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Register Name: RFDL Register Description: Receive FDL Register Register Address: C0h Bit # 7 6 Name RFDL7 RFDL6 Default 0 0 The receive FDL register (RFDL) reports the incoming FDL or the incoming Fs bits. The LSB is received first. ...
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Transmit Section The transmit section shifts out into the T1 data stream either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the transmit FDL register (TFDL). When a new ...
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LINE INTERFACE UNIT (LIU) The LIU contains three sections: the receiver that handles clock and data recovery, the transmitter that waveshapes and drives the T1 line, and the jitter attenuator. These three sections are controlled by the line interface ...
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Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI/HDB3 or T1 AMI/B8ZS waveform presented at the RTIP and RRING inputs. If the jitter attenuator is placed in the receive path (as ...
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Transmitter The DS2155 uses a phase-lock loop along with a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the line. The waveforms created by the DS2155 meet the latest ETSI, ITU, ANSI, ...
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MCLK Prescaler A 16.384MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz clock must be applied at MCLK. ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specifications require an accuracy of ±32ppm for T1 ...
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LIU Control Registers Register Name: LIC1 Register Description: Line Interface Control 1 Register Address: 78h Bit # 7 6 Name L2 L1 Default 0 0 Bit 0/Transmit Power-Down (TPD powers down the transmitter and tri-states the TTIP ...
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T1 Mode DSX-1 (0ft to 133ft) / 0dB CSU DSX-1 (133ft to 266ft DSX-1 (266ft to 399ft DSX-1 (399ft to 533ft DSX-1 ...
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Register Name: TLBC Register Description: Transmit Line Build-Out Control Register Address: 7Dh Bit # 7 6 Name - AGCE Default 0 0 Bit 0–5 Gain Control Bits 0–5 (GC0–GC5). The GC0 through GC5 bits control the gain setting for the ...
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Register Name: LIC2 Register Description: Line Interface Control 2 Register Address: 79h Bit # 7 6 Name ETS LIRST Default 0 0 Bit 0/Custom Line Driver Select (CLDS). Setting this bit redefines the operation of the transmit ...
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Register Name: LIC3 Register Description: Line Interface Control 3 Register Address: 7Ah Bit # 7 6 Name — TCES Default 0 0 Bit 0/Transmit Alternate Ones and Zeros (TAOZ). Transmit a …101010… pattern (customer disconnect indication signal) at TTIP and ...
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Register Name: LIC4 Register Description: Line Interface Control 4 Register Address: 7Bh Bit # 7 6 Name CMIE CMII Default 0 0 Bits 0, 1/Receive Termination Select (RT0, RT1) RT1 RT0 Internal Receive-Termination Configuration 0 0 Internal receive-side termination disabled ...
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Register Name: INFO2 Register Description: Information Register 2 Register Address: 11h Bit # 7 6 Name BSYNC BD Default 0 0 Bits 0 to 3/Receive Level Bits (RL0 to RL3). Real-time bits RL3 RL2 RL1 ...
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Register Name: SR1 Register Description: Status Register 1 Register Address: 16h Bit # 7 6 Name ILUT TIMER Default 0 0 Bit 0/Loss of Line-Interface Transmit-Clock Condition (LOLITC). Set when TCLKI has not transitioned for one channel time. This is ...
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Register Name: IMR1 Register Description: Interrupt Mask Register 1 Register Address: 17h Bit # 7 6 Name ILUT TIMER Default 0 0 Bit 0/Loss-of-Transmit Clock Condition (LOLITC interrupt masked 1 = interrupt enabled—generates interrupts on rising and falling ...
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Recommended Circuits Figure 24-3. Software-Selected Termination, Metallic Protection F1 75/100/110/120 Ω isted Pair/Coax F2 75/100/110/120 Ω isted Pair/Coax Design Notes: 1 Choke is optional but should be included when necessary f or common mode noise ...
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Figure 24-4. Software-Selected Termination, Longitudinal Protection F1 100/110/120 Ω isted Pair F2 F3 100/110/120 Ω isted Pair F4 Design Notes: 1 Choke is optional but should be included when necessary f or common mode noise reduction. ...
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Component Specifications Table 24-C. Transformer Specifications SPECIFICATION Turns Ratio 3.3V Applications Primary Inductance Leakage Inductance Intertwining Capacitance Transmit Transformer DC Resistance Primary (Device Side) Secondary Receive Transformer DC Resistance Primary (Device Side) Secondary RECOMMENDED VALUE 1:1 (receive) and 1:2 ...
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Figure 24-5. E1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 Figure 24-6. T1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ...
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Figure 24-7. Jitter Tolerance 1k 100 10 1 0.1 1 Figure 24-8. Jitter Tolerance (E1 Mode) 1k 100 0.1 1 DS2155 TOLERANCE TR 62411 (DEC. 90) ITU-T G.823 10 100 1k FREQUENCY (Hz) DS2155 TOLERANCE 1.5 MINIMUM ...
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Figure 24-9. Jitter Attenuation (T1 Mode) 0dB -20dB -40dB -60dB 1 Figure 24-10. Jitter Attenuation (E1 Mode) 0 -20 -40 -60 1 DS2155 T1 MODE 10 100 1K FREQUENCY (Hz) TBR12 Prohibited Area DS2155 E1 MODE 10 100 1k FREQUENCY ...
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Figure 24-11. Optional Crystal Connections Note 1: C1 and C2 should be 5pF lower than two times the nominal loading capacitance of the crystal to adjust for the input capacitance of the DS2155. DS2155 XTALD MCLK C1 C2 162 of ...
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PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION The DS2155 has the ability to generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. To ...
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Register Name: IBCC Register Description: In-Band Code Control Register Register Address: B6h Bit # 7 6 Name TC1 TC0 Default 0 0 Bits 0 to 2/Receive Down-Code Length Definition Bits (RDN0 to RDN2) RDN2 RDN1 ...
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Register Name: TCD1 Register Description: Transmit Code-Definition Register 1 Register Address: B7h Bit # 7 6 Name C7 C6 Default 0 0 Bit 0/Transmit Code-Definition Bit 0 (C0). A don’t care if a 5-, 6-, or 7-bit length is selected. ...
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Register Name: RUPCD1 Register Description: Receive Up-Code Definition Register 1 Register Address: B9h Bit # 7 6 Name C7 C6 Default 0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive Up-Code Definition Bits 0 (C0). A ...
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Register Name: RDNCD1 Register Description: Receive Down-Code Definition Register 1 Register Address: BBh Bit # 7 6 Name C7 C6 Default 0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive Down-Code Definition Bit 0 (C0). A ...
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Register Name: RSCC Register Description: In-Band Receive Spare Control Register Register Address: BDh Bit # 7 6 Name — — Default 0 0 Bits 0 to 2/Receive Spare Code Length Definition Bits (RSC0 to RSC2) RSC2 RSC1 RSC0 0 0 ...
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Register Name: RSCD1 Register Description: Receive Spare-Code Definition Register 1 Register Address: BEh Bit # 7 6 Name C7 C6 Default 0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive Spare-Code Definition Bit 0 (C0). A ...
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BERT FUNCTION The BERT block can generate and detect pseudorandom and repeating bit patterns used to test and stress data communication links, and it is capable of generating and detecting the following patterns: The pseudorandom patterns 2E7, ...
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Figure 26-1. Simplified Diagram of BERT in Network Direction FROM RECEIVE FRAMER PER-CHANNEL AND F-BIT (T1 MODE) MAPPING TO TRANSMIT FRAMER Figure 26-2. Simplified Diagram of BERT in Backplane Direction FROM RECEIVE FRAMER PER-CHANNEL AND F-BIT (T1 MODE) MAPPING TO ...
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BERT Register Descriptions Register Name: BC1 Register Description: BERT Control Register 1 Register Address: E0h Bit # 7 6 Name TC TINV Default 0 0 Bit 0/Force Resynchronization (RESYNC). A low-to-high transition forces the receive BERT synchronizer to resynchronize ...
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Register Name: BC2 Register Description: BERT Control Register 2 Register Address: E1h Bit # 7 6 Name EIB2 EIB1 Default 0 0 Bits 0 to 3/Repetitive Pattern Length Bit 3 (RPL0 to RPL3). RPL0 is the LSB and RPL3 is ...
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Register Name: SR9 Register Description: Status Register 9 Register Address: 26h Bit # 7 6 Name — BBED Default 0 0 Bit 0/BERT in Synchronization Condition (BSYNC). Set when the incoming pattern matches for 32 consecutive bit positions. Refer to ...
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Register Name: IMR9 Register Description: Interrupt Mask Register 9 Register Address: 27h Bit # 7 6 Name — BBED Default 0 0 Bit 0/BERT in Synchronization Condition (BSYNC interrupt masked 1 = interrupt enabled—interrupts on rising and falling ...
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BERT Repetitive Pattern Set These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a pseudorandom pattern, alternating word pattern Daly pattern. For a repetitive pattern that is fewer than ...
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BERT Bit Counter Once BERT has achieved synchronization, this 32-bit counter increments for each data bit (i.e., clock) received. Toggling the LC control bit in BC1 can clear this counter. This counter saturates when full and sets the BBCO ...
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BERT Error Counter Once BERT has achieved synchronization, this 24-bit counter increments for each data bit received in error. Toggling the LC control bit in BC1 can clear this counter. This counter saturates when full and sets the BECO ...
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Register Name: BIC Register Description: BERT Interface Control Register Register Address: EAh Bit # 7 6 Name — RFUS Default 0 0 Bit 0/BERT Enable (BERTEN BERT disabled 1 = BERT enabled Bit 1/BERT Direction (BERTDIR ...
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PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY) An error-insertion function is available in the DS2155 and is used to create errors in the payload portion of the T1 frame in the transmit path. This function is only available in T1 ...
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Register Name: ERC Register Description: Error-Rate Control Register Register Address: EBh Bit # 7 6 Name WNOE — Default 0 0 Bits 0 to 3/Error-Insertion Rate Select Bits (ER0 to ER3) ER3 ER2 ER1 ER0 ...
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Number-of-Errors Registers The number-of-error registers determine how many errors are generated 1023 errors can be generated. The host loads the number of errors to be generated into the NOE1 and NOE2 registers. The host can also update ...
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Number-of-Errors Left Register The host can read the NOELx registers at any time to determine how many errors are left to be inserted. Register Name: NOEL1 Register Description: Number-of-Errors Left 1 Register Address: EEh Bit # 7 6 Name ...
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INTERLEAVED PCM BUS OPERATION (IBO) In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses to simplify transport across the system backplane. The DS2155 can be configured to allow PCM data to be ...
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Register Name: IBOC Register Description: Interleave Bus Operation Control Register Register Address: C5h Bit # 7 6 Name — IBS1 Default 0 0 Bits 0 to 2/Device Assignment Bits (DA0 to DA2) DA2 DA1 DA0 ...
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Figure 28-1. IBO Example RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG TSER DS2155 #1 RSER RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG TSER DS2155 #2 RSER RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG TSER DS2155 #3 RSER RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG ...
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EXTENDED SYSTEM INFORMATION BUS (ESIB) The extended system information bus (ESIB) allows up to eight DS2155s to share an 8-bit CPU bus for reporting alarms and interrupt status as a group. With a single bus read, the host can ...
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Register Name: ESIBCR1 Register Description: Extended System Information Bus Control Register 1 Register Address: B0h Bit # 7 6 Name — — Default 0 0 Bit 0/Extended System Information Bus Enable (ESIEN disabled 1 = enabled Bits 1 ...
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Register Name: ESIBCR2 Register Description: Extended System Information Bus Control Register 2 Register Address: B1h Bit # 7 6 Name — ESI4SEL2 Default 0 0 Bits 0 to 2/Address ESI3 Data Output Select (ESI3SEL0 to ESI3SEL2). These bits select what ...
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Register Name: ESIB1 Register Description: Extended System Information Bus Register 1 Register Address: B2h Bit # 7 6 Name DISn DISn Default 0 0 Bits 0 to 7/Device Interrupt Status (DISn). Causes all devices participating in the ESIB group to ...
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PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER The DS2155 contains an on-chip clock synthesizer that generates a user-selectable clock output on the BPCLK pin, referenced to the recovered receive clock (RCLK). The synthesizer uses a phase-locked loop to generate low-jitter clocks. Common ...
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Register Name: CCR3 Register Description: Common Control Register 3 Register Address: 72h Bit # 7 6 Name TMSS INTDIS Default 0 0 Bit 0/Receive Gapped-Clock Enable (RGPCKEN RCHCLK functions normally 1 = enable gapped bit-clock output on RCHCLK ...
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USER-PROGRAMMABLE OUTPUT PINS The DS2155 provides four user-programmable output pins. The pins are automatically cleared power- result of a hardware- or software-issued reset. Register Name: CCR4 Register Description: Common Control Register 4 Register ...
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TRANSMIT FLOW DIAGRAMS Figure 33-1. T1 Transmit Flow Diagram HSIE1-3 through PCPR ESCR.4 TESE LBCR1.1 PLB TLINK H1TC.4 HDLC FDL #1 THMS1 H2TC.4 HDLC FDL #2 THMS2 TFDL Tx FDL T1TCR2.5 Zero TZSE Stuffer T1TCR1.2 FDL Mux TFDLS BOC ...
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From BOC Mux T1TCR2.3 FBCT1 T1TCR2.4 FBCT2 NOEL != 0 ERC.4 CE PEICS1-3 T1CCR1.1 PDE CRC Calculation T1TCR2.7 B8ZSE T1TCR1.1 TBL IOCR1.0 ODF CCR1.4 ODM From ESF Yellow Alarm FDL Mux ESF Yellow CRC Mux D4 bit 2 BERT Yellow ...
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Figure 33-2. E1 Transmit Flow Diagram HSIE1-4 through PCPR ESCR.4 TESE LBCR1.1 PLB KEY - PIN - SELECTOR - REGISTER TSER TSIG Hardware Signaling TX ESTORE Estore Mux TESO Off-Chip Connection TDATA RDATA From E1_rcv_logic Payload HDLC Loopback Mux Engine ...
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From Idle Code Mux Per-Channel TNAF Sa-bit Mux Si-bit Mux E1TCR1.4 TSIS E1TCR1.0 TCRC4 Si/CRC4 Mux Auto E- E1TCR2.2 AEBE bit Gen Sa4S - Sa8S E1TCR2.5 - E1TCR2.7 E1TCR2.8 ARA TSaCR SSIE1-4 E1TCR1.0 T16S E1TCR1.0 TCRC4 CCR1.6 CRC4R E1TCR2.1 AAIS ...
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From HDB3 Encoding Mux Bipolar/ NRZ IOCR1.0 ODF coding RPOS RLB Mux CCR1.4 ODM TPOS FLB LBCR1.0 FLB TO RECEIVER Select RNEG RLB Mux RLB LBCR1.2 1/2 CLK/ FULL CLK TNEG 198 of 238 E1 TRANSMIT FLOW DIAGRAM ...
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JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT 34.1 Description The DS2155 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGH-Z, CLAMP, and IDCODE (Figure 34-1.). The DS2155 contains the ...
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TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK (Figure 34-2). Test-Logic-Reset Upon power-up, the TAP controller is in the Test-Logic-Reset state. The ...