DS2153QN-A7/T&R Maxim Integrated, DS2153QN-A7/T&R Datasheet

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DS2153QN-A7/T&R

Manufacturer Part Number
DS2153QN-A7/T&R
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS2153QN-A7/T&R

Product
Framer
Number Of Transceivers
1
Supply Current (max)
65 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
PLCC-44
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
5 V
Supply Voltage - Max
5.25 V
Supply Voltage - Min
4.8 V
Part # Aliases
90-2153Q-NT7
www.maxim-ic.com
FEATURES
ORDERING INFORMATION
+
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
DS2153Q
DS2153Q+
DS2153QN
DS2153QN+
Denotes lead-free/RoHS-compliant package.
Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceiver Functionality
On-Board Line Interface for Clock/Data
Recovery and Waveshaping
32-Bit or 128-Bit Jitter Attenuator
Generates Line Build-Outs for Both 120Ω
and 75Ω Lines
Frames to FAS, CAS, and CRC4 Formats
Dual On-Board Two-Frame Elastic Store Slip
Buffers That can Connect to Backplanes Up
to 8.192MHz
8-Bit Parallel Control Port That can be Used
on Either Multiplexed or Nonmultiplexed
Buses
Extracts and Inserts CAS Signaling
Detects and Generates Remote and AIS
Alarms
Programmable Output Clocks for Fractional
E1, H0, and H12 Applications
Fully Independent Transmit and Receive
Functionality
Full Access to Both Si and Sa Bits
Three Separate Loopbacks for Testing
Large Counters for Bipolar and Code
Violations, CRC4 Codeword Errors, FAS
Errors, and E Bits
Pin Compatible with DS2151Q T1 Single-
Chip Transceiver
5V Supply; Low-Power CMOS
PART
-40°C to +85°C 44 PLCC
-40°C to +85°C 44 PLCC
0°C to +70°C
0°C to +70°C
RANGE
TEMP
44 PLCC
44 PLCC
PIN-
PACKAGE
1 of 60
PIN CONFIGURATION
RLOS/LOTC
E1 Single-Chip Transceiver
WR (R/W)
RCHCLK
SYSCLK
ALE(AS)
RSYNC
DS2153Q
RLCLK
RLINK
T1SCT
DVSS
RSER
RCLK
Dallas
7
8
9
10
11
12
13
14
15
16
17
ACTUAL SIZE OF 44-PIN PLCC
FUNCTIONAL BLOCKS
PARALLEL CONTROL
DS2153Q
PLCC
PORT
DS2153Q
38
37
36
35
34
33
32
31
30
29
39
REV: 01106
TSER
TCLK
DVDD
TSYNC
TLINK
TLCLK
TCHBLK
TRING
TVDD
TVSS
TTIP

Related parts for DS2153QN-A7/T&R

DS2153QN-A7/T&R Summary of contents

Page 1

... DS2153Q+ 0°C to +70°C DS2153QN -40°C to +85°C 44 PLCC DS2153QN+ -40°C to +85°C 44 PLCC + Denotes lead-free/RoHS-compliant package. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. ...

Page 2

DETAILED DESCRIPTION....................................................................................................4 1.1 I ................................................................................................................................ 4 NTRODUCTION 1.2 R ’ N .............................................................................................................................. 4 EADER S OTE 2 PIN DESCRIPTION................................................................................................................6 2.1 DS2153Q R M EGISTER 3 PARALLEL PORT .................................................................................................................9 4 CONTROL AND TEST REGISTERS...................................................................................10 4 ......................................................................................................................... 17 OCAL ...

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Figure 1-1. DS2153Q Block Diagram ......................................................................................................... 5 Figure 13-1. External Analog Connections............................................................................................... 43 Figure 13-2. Jitter Tolerance .................................................................................................................... 44 Figure 13-3. Transmit Waveform Template .............................................................................................. 44 Figure 13-4. Jitter Attenuation .................................................................................................................. 45 Figure 14-1. Receive Side Timing ............................................................................................................ 46 Figure ...

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DETAILED DESCRIPTION The DS2153Q E1 single-chip transceiver (SCT) contains all the necessary functions for connection to E1 lines. The on-board clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ serial stream. The DS2153Q automatically adjusts to E1 ...

Page 5

Figure 1-1. DS2153Q Block Diagram ...

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PIN DESCRIPTION PIN NAME TYPE 1–4, AD4–AD7, 41–44 AD0–AD3 5 (DS ALE(AS) ( RLINK 10 RLCLK 11 DVSS 12 RCLK 13 RCHCLK 14 RSER 15 RSYNC 16 RLOS/LOTC 17 SYSCLK ...

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PIN NAME TYPE 20 BTS I RTIP, 21, 22 — RRING 23 RVDD — 24 RVSS — XTAL1, 25, 26 — XTAL2 27 O INT1 28 O INT2 29 TTIP — 30 TVSS — 31 TVDD — 32 TRING — ...

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DS2153Q Register Map ADDRESS R/W REGISTER NAME 00 R BPV or Code Violation Count BPV or Code Violation Count CRC4 Count 1/FAS Error Count CRC4 Error Count ...

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PARALLEL PORT The DS2153Q is controlled via a multiplexed bidirectional address/data bus by an external microcontroller or microprocessor. The DS2153Q can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing ...

Page 10

CONTROL AND TEST REGISTERS The operation of the DS2153Q is configured via a set of seven registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS2153Q has been initialized, the control ...

Page 11

Table 4-1. Sync/Resync Criteria FRAME OR MULTIFRAME SYNC CRITERIA LEVEL FAS present in frames N and and FAS not FAS present in frame Two valid MF alignment words found within 8ms. CRC4 Valid MF ...

Page 12

TCR1: TRANSMIT CONTROL REGISTER 1 (Address = 12 Hex) (MSB) — TFPT SYMBOL POSITION — TCR1.7 TFPT TCR1.6 T16S TCR1.5 TUA1 TCR1.4 TSiS TCR1.3 TSA1 TCR1.2 TSM TCR1.1 TSIO TCR1.0 Note: For details about how the Transmit Control Registers affect ...

Page 13

TCR2: TRANSMIT CONTROL REGISTER 2 (Address = 13 Hex) (MSB) Sa8S Sa7S SYMBOL POSITION Sa8S TCR2.7 Sa7S TCR2.6 Sa6S TCR2.5 Sa5S TCR2.4 Sa4S TCR2.3 — TCR2.2 AEBE TCR2.1 P16F TCR2.0 Sa6S Sa5S Sa4S NAME AND DESCRIPTION Sa8 Bit Select. Set ...

Page 14

CCR1: COMMON CONTROL REGISTER 1 (Address = 14 Hex) (MSB) FLB THDB3 TG802 SYMBOL POSITION FLB CCR1.7 THDB3 CCR1.6 TG802 CCR1.5 TCRC4 CCR1.4 RSM CCR1.3 RHDB3 CCR1.2 RG802 CCR1.1 RCRC4 CCR1.0 TCRC4 RSM RHDB3 NAME AND DESCRIPTION Framer Loopback. 0 ...

Page 15

CCR2: COMMON CONTROL REGISTER 2 (Address = 1A Hex) (MSB) ECUS VCRFS SYMBOL POSITION ECUS CCR2.7 VCRFS CCR2.6 AAIS CCR2.5 ARA CCR2.4 RSERC CCR2.3 LOTCMC CCR2.2 RLB CCR2.1 LLB CCR2.0 AAIS ARA RSERC NAME AND DESCRIPTION Error Counter Update Select. ...

Page 16

CCR3: COMMON CONTROL REGISTER 3 (Address = 1B Hex) (MSB) TESE TCBFS TIRFS SYMBOL POSITION TESE CCR3.7 TCBFS CCR3.6 TIRFS CCR3.5 ESR CCR3.4 LIRST CCR3.3 — CCR3.2 TSCLKM CCR3.1 — CCR3.0 ESR LIRST NAME AND DESCRIPTION Transmit Elastic Store Enable. ...

Page 17

Local Loopback When CCR2.0 is set the DS2153Q will be forced into Local Loopback (LLB). In this loopback, data will continue to be transmitted as normal through the transmit side of the SCT. Data being received ...

Page 18

STATUS AND INFORMATION REGISTERS There is a set of four registers that contain information on the current real-time status of the DS2153Q: Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer Status Register (SSR). ...

Page 19

RIR: RECEIVE INFORMATION REGISTER (Address = 08 Hex) (MSB) TESF TESE SYMBOL POSITION TESF RIR.7 TESE RIR.6 JALT RIR.5 RESF RIR.4 RESE RIR.3 CRCRC RIR.2 FASRC RIR.1 CASRC RIR.0 JALT RESF RESE NAME AND DESCRIPTION Transmit Elastic Store Full. Set ...

Page 20

SSR: SYNCHRONIZER STATUS REGISTER (Address = 1E Hex) (MSB) CSC5 CSC4 SYMBOL POSITION CSC5 SSR.7 CSC4 SSR.6 CSC3 SSR.5 CSC2 SSR.4 CSC0 SSR.3 FASSA SSR.2 CASSA SSR.1 CRC4SA SSR.0 5.1 CRC4 Sync Counter The CRC4 sync counter increments each time ...

Page 21

SR1: STATUS REGISTER 1 (Address = 06 Hex) (MSB) RSA1 RDMA SYMBOL POSITION RSA1 SR1.7 RDMA SR1.6 RSA0 SR1.5 RSLIP SR1.4 RUA1 SR1.3 RRA SR1.2 RCL SR1.1 RLOS SR1.0 RSA0 RSLIP RUA1 NAME AND DESCRIPTION Receive Signaling All 1s. Set ...

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Table 5-1. Alarm Set and Clear Criteria ALARM RSA1 Over 16 consecutive frames (one full MF) time slot 16 contains less than (receive signaling three 0s all 1s) RSA0 Over 16 consecutive frames (one full MF) time slot 16 contains ...

Page 23

SR2: STATUS REGISTER 2 (Address = 07 Hex) (MSB) RMF RAF SYMBOL POSITION RMF SR2.7 RAF SR2.6 TMF SR2.5 SEC SR2.4 TAF SR2.3 LOTC SR2.2 RCMF SR2.1 TSLIP SR2.0 TMF SEC TAF NAME AND DESCRIPTION Receive CAS Multiframe. Set every ...

Page 24

IMR1: INTERRUPT MASK REGISTER1 (Address = 16 Hex) (MSB) RSA1 RDMA SYMBOL POSITION RSA1 IMR1.7 RDMA IMR1.6 RSA0 IMR1.5 RSLIP IMR1.4 RUA1 IMR1.3 RRA IMR1.2 RCL IMR1.1 RLOS IMR1.0 RSA0 RSLIP RUA1 NAME AND DESCRIPTION Receive Signaling All 1s. 0 ...

Page 25

IMR2: INTERRUPT MASK REGISTER 2 (Address = 17 Hex) (MSB) RMF RAF SYMBOL POSITION RMF IMR2.7 RAF IMR2.6 TMF IMR2.5 SEC IMR2.4 TAF IMR2.3 LOTC IMR2.2 RCMF IMR2.1 TSLIP IMR2.0 TMF SEC TAF NAME AND DESCRIPTION Receive CAS Multiframe. 0 ...

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ERROR COUNT REGISTERS There are a set of four counters in the DS2153Q that record bipolar or code violations, errors in the CRC4 SMF codewords, E bits as reported by the far end, and word errors in the FAS. ...

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CRC4 Error Counter CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word of a 10-bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the maximum CRC4 ...

Page 28

FAS Bit Error Counter FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word of a 12-bit counter that records word errors in the Frame Alignment Signal in time slot 0. This ...

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Sa DATA LINK CONTROL AND OPERATION The DS2153Q provides for access to the proposed E1 performance monitor data link in the Sa bit positions. The device allows access to the Sa bits either via a set of two internal ...

Page 30

SIGNALING OPERATION The Channel Associated Signaling (CAS) bits embedded in the E1 stream can be extracted from the receive stream and inserted into the transmit stream by the DS2153Q. Each of the 30 channels has four signaling bits (A/B/C/D) ...

Page 31

TS1 TO TS16: TRANSMIT SIGNALING REGISTERS (Address = Hex) (MSB A(1) B(1) C(1) A(2) B(2) C(2) A(3) B(3) C(3) A(4) B(4) C(4) A(5) B(5) C(5) A(6) B(6) C(6) A(7) B(7) C(7) A(8) B(8) C(8) ...

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TRANSMIT IDLE REGISTERS There is a set of five registers in the DS2153Q that can be used to custom tailor the data that transmitted onto the E1 line channel-by-channel basis. Each of the 32 ...

Page 33

CLOCK BLOCKING REGISTERS The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either high or low ...

Page 34

TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3 (MSB) CH20 CH4 CH19 CH24 CH8 CH23 CH28 CH12 CH27 CH32 CH16 CH31 * CH1 and CH17 should be set allow the internal TS1 register to create the CAS Multiframe Alignment ...

Page 35

ELASTIC STORES OPERATION The DS2153Q has an on-board two-frame (512 bits) elastic store. This elastic store can be enabled via RCR2.1. If the elastic store is enabled (RCR2.1=1), then the user must provide either a 1.544MHz (RCR2 ...

Page 36

ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION The DS2153Q provides for access to both the Additional (Sa) and International (Si) bits. On the receive side, the RAF and RNAF registers will always report the data as it received in ...

Page 37

RNAF: RECEIVE NON-ALIGN FRAME REGISTER (Address = 1F Hex) (MSB SYMBOL POSITION Si RNAF.7 1 RNAF.6 A RNAF.5 Sa4 RNAF.4 Sa5 RNAF.3 Sa6 RNAF.2 Sa7 RNAF.1 Sa8 RNAF.0 TAF: TRANSMIT ALIGN FRAME REGISTER (Address = 20 Hex) (MSB) ...

Page 38

TNAF: TRANSMIT NON-ALIGN FRAME REGISTER (Address = 21 Hex) (MSB SYMBOL POSITION Si TNAF.7 1 TNAF.6 A TNAF.5 Sa4 TNAF.4 Sa5 TNAF.3 Sa6 TNAF.2 Sa7 TNAF.1 Sa8 TNAF.0 A Sa4 Sa5 NAME AND DESCRIPTION International Bit. Frame Non-Alignment ...

Page 39

LINE INTERFACE FUNCTIONS The line interface function in the DS2153Q contains three sections: the receiver, which handles clock and data recovery; the transmitter, which waveshapes and drives the T1 line; and the jitter attenuator. Each of these three sections ...

Page 40

Receive Clock and Data Recovery The DS2153Q contains a digital clock recovery system. See The DS2153Q couples to the receive E1 twisted pair or coax via a 1:1 transformer. See transformer details. The DS2153Q automatically adjusts to the E1 ...

Page 41

Transmit Waveshaping and Line Driving The DS2153Q uses a set of laser-trimmed delay lines along with a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the E1 line. The waveforms created by the DS2153Q meet ...

Page 42

Jitter Attenuator The DS2153Q contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits via the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in ...

Page 43

Figure 13-1. External Analog Connections NOTE 1: ALL RESISTOR VALUES ARE ±1%. NOTE 2: THE R RESISTORS ARE USED TO INCREASE THE TRANSMITTER RETURN LOSS OR TO PROTECT THE DEVICE FROM T OVERVOLTAGE. NOTE 3: THE RR RESISTORS ARE USED ...

Page 44

Figure 13-2. Jitter Tolerance Figure 13-3. Transmit Waveform Template ...

Page 45

Figure 13-4. Jitter Attenuation ...

Page 46

TIMING DIAGRAMS Figure 14-1. Receive Side Timing NOTE 1: RSYNC IN THE FRAME MODE (RCR1.6 = 0). NOTE 2: RSYNC IN THE MULTIFRAME MODE (RCR1.6 = 1). NOTE 3: RLCLK IS PROGRAMMED TO OUTPUT JUST THE Sa4 BIT. NOTE ...

Page 47

Figure 14-3. 1.544MHz Boundary Timing with Elastic Store(s) Disabled NOTE 1: DATA FROM THE E1 CHANNELS 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1 LINK IS MAPPED TO CHANNEL 1 OF THE ...

Page 48

Figure 14-5. Transmit Side Timing NOTE 1: TSYNC IN THE FRAME MODE (TCR1.1 = 0). NOTE 2: TSYNC IN THE MULTIFRAME MODE (TCR1.1 = 1). NOTE 3: TLINK IS PROGRAMMED TO SOURCE ONLY THE Sa4 BIT. NOTE 4: THIS DIAGRAM ...

Page 49

Figure 14-7. G.802 Timing NOTE 1: RCHBLK OR TCHBLK IS PROGRAMMED TO PULSE HIGH DURING TIME SLOTS 25, AND DURING BIT 1 OF TIME SLOT 26 ...

Page 50

Figure 14-8. Synchronization Flowchart ...

Page 51

Figure 14-9. Transmit Data Flow NOTE 1: TCLK MUST BE TIED TO RCLK (OR SYSCLK IF THE ELASTIC STORE IS ENABLED) AND TSYNC MUST BE TIED TO RSYNC FOR DATA TO BE PROPERLY SOURCED FROM RSER ...

Page 52

... PARAMETER Supply Current at 5V Input Leakage Output Leakage Output Current (2.4V) Output Current (0.4V) NOTES: 1) Applies to RVDD, TVDD, and DVDD. 2) TCLK =2.048MHz < V < Applies to and INT1 INT1 = -40°C to +85°C for DS2153QN.) A SYMBOL MIN V 2 -0 4.80 SYMBOL MIN C IN ...

Page 53

... AC CHARACTERISTICS Table 16-1. AC Characteristics—Parallel Port = 5V ±5 0°C to +70°C for DS2153Q DS2153QN.) (See Figure 16-1, PARAMETER Cycle Time Pulse Width, DS Low or RD High Pulse Width, DS High or RD Low Input Rise/Fall Times R/ Hold Time W R/ Setup Time before DS W High ...

Page 54

Figure 16-1. Intel Bus Read AC Timing Figure 16-2. Intel Bus Write AC Timing ...

Page 55

Figure 16-3. Motorola Bus AC Timing ...

Page 56

... Table 16-2. AC Characteristics—Receive Side = 5V ±5 0°C to +70°C for DS2153Q DS2153QN.) (See Figure 16-4.) PARAMETER ACLKI/RCLK Period RCLK Pulse Width RCLK Pulse Width SYSCLK Period SYSCLK Pulse Width RSYNC Setup to SYSCLK Falling RSYNC Pulse Width SYSCLK Rise/Fall Times Delay RCLK or SYSCLK to ...

Page 57

Figure 16-4. Receive Side AC Timing NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR1.5 = 0). NOTE 2: RSYNC IS IN THE INPUT MODE (RCR1.5 = 1). NOTE 3: RLCLK AND RLINK ONLY HAVE A TIMING RELATIONSHIP TO RCLK. ...

Page 58

... Table 16-3. AC Characteristics—Transmit Side = 5V ±5 0°C to +70°C for DS2153Q DS2153QN.) (See Figure 16-5.) PARAMETER TCLK Period TCLK Pulse Width TSER and TLINK Set up to TCLK Falling TSER and TLINK Hold from TCLK Falling TSYNC Set up to TCLK Falling TSYNC Pulse Width ...

Page 59

Figure 16-5. Transmit Side AC Timing NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR1.0 = 1). NOTE 2: TSYNC IS IN THE INPUT MODE (TCR1.0 = 0). NOTE 3: NO TIMING RELATIONSHIP BETWEEN TSYNC AND TLCLK/TLINK IS IMPLIED. NOTE ...

Page 60

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