DS2153Q-A7 Maxim Integrated, DS2153Q-A7 Datasheet
DS2153Q-A7
Specifications of DS2153Q-A7
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DS2153Q-A7 Summary of contents
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... PIN CONFIGURATION Dallas DS2153Q T1SCT ALE(AS) WR (R/W) RLINK RLCLK DVSS RCLK RCHCLK RSER RSYNC RLOS/LOTC SYSCLK PIN- PACKAGE 44 PLCC 44 PLCC DS2153Q FUNCTIONAL BLOCKS PARALLEL CONTROL PORT ACTUAL SIZE OF 44-PIN PLCC TSER 7 39 TCLK 8 38 DVDD 9 37 DS2153Q TSYNC 10 36 TLINK 35 11 ...
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... DETAILED DESCRIPTION....................................................................................................4 1.1 I ................................................................................................................................ 4 NTRODUCTION 1.2 R ’ N .............................................................................................................................. 4 EADER S OTE 2 PIN DESCRIPTION................................................................................................................6 2.1 DS2153Q R M EGISTER 3 PARALLEL PORT .................................................................................................................9 4 CONTROL AND TEST REGISTERS...................................................................................10 4 ......................................................................................................................... 17 OCAL OOPBACK 4 ...................................................................................................................... 17 EMOTE OOPBACK 4 ...................................................................................................................... 17 RAMER OOPBACK 4 UTOMATIC LARM ENERATION 4 OWER P EQUENCE 5 STATUS AND INFORMATION REGISTERS ......................................................................18 5 ...
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... Figure 1-1. DS2153Q Block Diagram ......................................................................................................... 5 Figure 13-1. External Analog Connections............................................................................................... 43 Figure 13-2. Jitter Tolerance .................................................................................................................... 44 Figure 13-3. Transmit Waveform Template .............................................................................................. 44 Figure 13-4. Jitter Attenuation .................................................................................................................. 45 Figure 14-1. Receive Side Timing ............................................................................................................ 46 Figure 14-2. Receive Side Boundary Timing (with Elastic Stores Disabled) ............................................ 46 Figure 14-3. 1.544MHz Boundary Timing with Elastic Store(s) Disabled ................................................. 47 Figure 14-4. 2.048MHz Boundary Timing with Elastic Store(s) Enabled.................................................. 47 Figure 14-5 ...
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... The transmit formatter will provide the necessary data overhead for E1 transmission. Once the data stream has been prepared for transmission sent via the jitter attenuation mux to the waveshaping and line driver functions. The DS2153Q will drive the E1 line from the TTIP and TRING pins via a coupling transformer. ...
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... Figure 1-1. DS2153Q Block Diagram ...
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PIN DESCRIPTION PIN NAME TYPE 1–4, AD4–AD7, 41–44 AD0–AD3 5 (DS ALE(AS) ( RLINK 10 RLCLK 11 DVSS 12 RCLK 13 RCHCLK 14 RSER 15 RSYNC 16 RLOS/LOTC 17 SYSCLK ...
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... Transmit Link Data. If enabled, this pin will be sampled on the falling edge of TCLK to insert the Sa bits. See Section Transmit Sync. A pulse at this pin will establish either frame or multiframe boundaries for the DS2153Q. Via TCR1.1, the DS2153Q can be programmed to output either a frame or multiframe pulse at this pin. See Section 14 for timing details ...
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... DS2153Q Register Map ADDRESS R/W REGISTER NAME 00 R BPV or Code Violation Count BPV or Code Violation Count CRC4 Count 1/FAS Error Count CRC4 Error Count E-Bit Count 1/FAS Error Count E-Bit Count Status Status 2 08 R/W Receive Information ...
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... AD0 to AD7 pins. Valid write data must be present and held stable during the later portion of the DS or pulses read cycle, the DS2153Q outputs a byte of data during the latter portion of the pulses. The read cycle is terminated and the bus returns to a high-impedance state as RD high in Intel timing transitions low in Motorola timing ...
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... Common Control Registers (CCR1, CCR2, and CCR3). Each of the seven registers is described in this section. The LICR is described in Section 13. The Test Registers at addresses 15 and 19 hex are used by the factory in testing the DS2153Q. On power- up, the Test Registers should be set to 00 hex in order for the DS2153Q to operate properly. ...
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Table 4-1. Sync/Resync Criteria FRAME OR MULTIFRAME SYNC CRITERIA LEVEL FAS present in frames N and and FAS not FAS present in frame Two valid MF alignment words found within 8ms. CRC4 Valid MF ...
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... TSiS TCR1.3 TSA1 TCR1.2 TSM TCR1.1 TSIO TCR1.0 Note: For details about how the Transmit Control Registers affect the operation of the DS2153Q, see Figure 14-9. T16S TUA1 TSiS NAME AND DESCRIPTION Not Assigned. Should be set to 0 when written to. Transmit Time Slot 0 Pass Through. ...
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TCR2: TRANSMIT CONTROL REGISTER 2 (Address = 13 Hex) (MSB) Sa8S Sa7S SYMBOL POSITION Sa8S TCR2.7 Sa7S TCR2.6 Sa6S TCR2.5 Sa5S TCR2.4 Sa4S TCR2.3 — TCR2.2 AEBE TCR2.1 P16F TCR2.0 Sa6S Sa5S Sa4S NAME AND DESCRIPTION Sa8 Bit Select. Set ...
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CCR1: COMMON CONTROL REGISTER 1 (Address = 14 Hex) (MSB) FLB THDB3 TG802 SYMBOL POSITION FLB CCR1.7 THDB3 CCR1.6 TG802 CCR1.5 TCRC4 CCR1.4 RSM CCR1.3 RHDB3 CCR1.2 RG802 CCR1.1 RCRC4 CCR1.0 TCRC4 RSM RHDB3 NAME AND DESCRIPTION Framer Loopback. 0 ...
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CCR2: COMMON CONTROL REGISTER 2 (Address = 1A Hex) (MSB) ECUS VCRFS SYMBOL POSITION ECUS CCR2.7 VCRFS CCR2.6 AAIS CCR2.5 ARA CCR2.4 RSERC CCR2.3 LOTCMC CCR2.2 RLB CCR2.1 LLB CCR2.0 AAIS ARA RSERC NAME AND DESCRIPTION Error Counter Update Select. ...
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CCR3: COMMON CONTROL REGISTER 3 (Address = 1B Hex) (MSB) TESE TCBFS TIRFS SYMBOL POSITION TESE CCR3.7 TCBFS CCR3.6 TIRFS CCR3.5 ESR CCR3.4 LIRST CCR3.3 — CCR3.2 TSCLKM CCR3.1 — CCR3.0 ESR LIRST NAME AND DESCRIPTION Transmit Elastic Store Enable. ...
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... BPVs that might have occurred intact) via the TTIP and TRING pins. Data will continue to pass through the receive side of the DS2153Q as it would normally and the data at the TSER input will be ignored. Data in this loopback will pass through the jitter attenuator. See 4 ...
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... The user will always precede a read of the SR1, SR2, and RIR registers with a write. The byte written to the register will inform the DS2153Q which bits the user wishes to read and have cleared. The user will write a byte to one of these three registers, with the bit positions he or she wishes to read and the bit positions he or she does not wish to obtain the latest information on ...
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RIR: RECEIVE INFORMATION REGISTER (Address = 08 Hex) (MSB) TESF TESE SYMBOL POSITION TESF RIR.7 TESE RIR.6 JALT RIR.5 RESF RIR.4 RESE RIR.3 CRCRC RIR.2 FASRC RIR.1 CASRC RIR.0 JALT RESF RESE NAME AND DESCRIPTION Transmit Elastic Store Full. Set ...
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... DS2153Q has successfully obtained synchronization at the CRC4 level. The counter can also be cleared by disabling the CRC4 mode (CCR1.0 = 0). This counter is useful for determining the amount of time the DS2153Q has been searching for synchronization at the CRC4 level. Annex B of CCITT G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400ms, then the search should be abandoned and proper action taken ...
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SR1: STATUS REGISTER 1 (Address = 06 Hex) (MSB) RSA1 RDMA SYMBOL POSITION RSA1 SR1.7 RDMA SR1.6 RSA0 SR1.5 RSLIP SR1.4 RUA1 SR1.3 RRA SR1.2 RCL SR1.1 RLOS SR1.0 RSA0 RSLIP RUA1 NAME AND DESCRIPTION Receive Signaling All 1s. Set ...
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Table 5-1. Alarm Set and Clear Criteria ALARM RSA1 Over 16 consecutive frames (one full MF) time slot 16 contains less than (receive signaling three 0s all 1s) RSA0 Over 16 consecutive frames (one full MF) time slot 16 contains ...
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SR2: STATUS REGISTER 2 (Address = 07 Hex) (MSB) RMF RAF SYMBOL POSITION RMF SR2.7 RAF SR2.6 TMF SR2.5 SEC SR2.4 TAF SR2.3 LOTC SR2.2 RCMF SR2.1 TSLIP SR2.0 TMF SEC TAF NAME AND DESCRIPTION Receive CAS Multiframe. Set every ...
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IMR1: INTERRUPT MASK REGISTER1 (Address = 16 Hex) (MSB) RSA1 RDMA SYMBOL POSITION RSA1 IMR1.7 RDMA IMR1.6 RSA0 IMR1.5 RSLIP IMR1.4 RUA1 IMR1.3 RRA IMR1.2 RCL IMR1.1 RLOS IMR1.0 RSA0 RSLIP RUA1 NAME AND DESCRIPTION Receive Signaling All 1s. 0 ...
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IMR2: INTERRUPT MASK REGISTER 2 (Address = 17 Hex) (MSB) RMF RAF SYMBOL POSITION RMF IMR2.7 RAF IMR2.6 TMF IMR2.5 SEC IMR2.4 TAF IMR2.3 LOTC IMR2.2 RCMF IMR2.1 TSLIP IMR2.0 TMF SEC TAF NAME AND DESCRIPTION Receive CAS Multiframe. 0 ...
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... ERROR COUNT REGISTERS There are a set of four counters in the DS2153Q that record bipolar or code violations, errors in the CRC4 SMF codewords, E bits as reported by the far end, and word errors in the FAS. Each of these four counters are automatically updated on either 1-second boundaries (CCR2 every 62.5ms (CCR2 ...
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CRC4 Error Counter CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word of a 10-bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the maximum CRC4 ...
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FAS Bit Error Counter FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word of a 12-bit counter that records word errors in the Frame Alignment Signal in time slot 0. This ...
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... TLINK pin. If the user wishes to pass the Sa bits through the DS2153Q without them being altered, then the device should be set up to source all five Sa bits via the TLINK pin and the TLINK pin should be tied to the TSER pin. See the timing diagrams and the ...
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... SIGNALING OPERATION The Channel Associated Signaling (CAS) bits embedded in the E1 stream can be extracted from the receive stream and inserted into the transmit stream by the DS2153Q. Each of the 30 channels has four signaling bits (A/B/C/D) associated with it. The numbers in parentheses are the channel associated with a particular signaling bit ...
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... TCR1.5. On multiframe boundaries, the DS2153Q will load the values present in the Transmit Signaling Register into an outgoing signaling shift register that is internal to the device. The user can utilize the Transmit Multiframe bit in Status Register 2 (SR2 ...
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... TRANSMIT IDLE REGISTERS There is a set of five registers in the DS2153Q that can be used to custom tailor the data that transmitted onto the E1 line channel-by-channel basis. Each of the 32 E1 channels can be forced to have a user-defined idle code inserted into them. TIR1/TIR2/TIR3/TIR4: TRANSMIT IDLE REGISTERS (Address = Hex) ...
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CLOCK BLOCKING REGISTERS The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either high or low ...
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TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3 (MSB) CH20 CH4 CH19 CH24 CH8 CH23 CH28 CH12 CH27 CH32 CH16 CH31 * CH1 and CH17 should be set allow the internal TS1 register to create the CAS Multiframe Alignment ...
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... ELASTIC STORES OPERATION The DS2153Q has an on-board two-frame (512 bits) elastic store. This elastic store can be enabled via RCR2.1. If the elastic store is enabled (RCR2.1=1), then the user must provide either a 1.544MHz (RCR2 2.048MHz (RCR2 clock at the SYSCLK pin. If the elastic store is enabled, then the user has the option of either providing a frame sync at the RSYNC pin (RCR1 ...
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... TAF and TNAF registers. It has 250µs to update the data or else the old data will be retransmitted. Data in the Si bit position will be overwritten if either the DS2153Q is programmed: (1) to source the Si bits from the TSER pin, (2) in the CRC4 mode, or (3) have automatic E-bit insertion enabled. Data in the Sa bit position will be overwritten if any of the TCR2 ...
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RNAF: RECEIVE NON-ALIGN FRAME REGISTER (Address = 1F Hex) (MSB SYMBOL POSITION Si RNAF.7 1 RNAF.6 A RNAF.5 Sa4 RNAF.4 Sa5 RNAF.3 Sa6 RNAF.2 Sa7 RNAF.1 Sa8 RNAF.0 TAF: TRANSMIT ALIGN FRAME REGISTER (Address = 20 Hex) (MSB) ...
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TNAF: TRANSMIT NON-ALIGN FRAME REGISTER (Address = 21 Hex) (MSB SYMBOL POSITION Si TNAF.7 1 TNAF.6 A TNAF.5 Sa4 TNAF.4 Sa5 TNAF.3 Sa6 TNAF.2 Sa7 TNAF.1 Sa8 TNAF.0 A Sa4 Sa5 NAME AND DESCRIPTION International Bit. Frame Non-Alignment ...
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... LINE INTERFACE FUNCTIONS The line interface function in the DS2153Q contains three sections: the receiver, which handles clock and data recovery; the transmitter, which waveshapes and drives the T1 line; and the jitter attenuator. Each of these three sections is controlled by the Line Interface Control Register (LICR), which is described below ...
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... Carrier Loss (RCL) condition will occur and the RCLK can be sourced from either the ACLKI pin or from the crystal attached to the XTAL1 and XTAL2 pins. The DS2153Q will sense the ACLKI pin to determine if a clock is present clock is applied to the ACLKI pin, then it should be tied to RVSS to prevent the device from falsely sensing a clock ...
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... N.M. = not meaningful Due to the nature of the design of the transmitter in the DS2153Q, very little jitter (less than 0.005UI broadband from 10Hz to 100kHz) is added to the jitter present on TCLK. Also, the waveforms that they create are independent of the duty cycle of TCLK. The transmitter in the DS2153Q couples to the E1 transmit shielded twisted pair or coax via a 1:1 ...
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... E1 signal. If the incoming jitter exceeds either 120UI is 32 bits), then the DS2153Q will divide the attached crystal by either 3.5 or 4.5 instead of the normal 4 to keep the buffer from overflowing. When the device divides by either 3.5 or 4.5, it also sets the Jitter Attenuator Limit Trip (JALT) bit in the Receive Information Register (RIR ...
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Figure 13-1. External Analog Connections NOTE 1: ALL RESISTOR VALUES ARE ±1%. NOTE 2: THE R RESISTORS ARE USED TO INCREASE THE TRANSMITTER RETURN LOSS OR TO PROTECT THE DEVICE FROM T OVERVOLTAGE. NOTE 3: THE RR RESISTORS ARE USED ...
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Figure 13-2. Jitter Tolerance Figure 13-3. Transmit Waveform Template ...
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Figure 13-4. Jitter Attenuation ...
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TIMING DIAGRAMS Figure 14-1. Receive Side Timing NOTE 1: RSYNC IN THE FRAME MODE (RCR1.6 = 0). NOTE 2: RSYNC IN THE MULTIFRAME MODE (RCR1.6 = 1). NOTE 3: RLCLK IS PROGRAMMED TO OUTPUT JUST THE Sa4 BIT. NOTE ...
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Figure 14-3. 1.544MHz Boundary Timing with Elastic Store(s) Disabled NOTE 1: DATA FROM THE E1 CHANNELS 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1 LINK IS MAPPED TO CHANNEL 1 OF THE ...
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Figure 14-5. Transmit Side Timing NOTE 1: TSYNC IN THE FRAME MODE (TCR1.1 = 0). NOTE 2: TSYNC IN THE MULTIFRAME MODE (TCR1.1 = 1). NOTE 3: TLINK IS PROGRAMMED TO SOURCE ONLY THE Sa4 BIT. NOTE 4: THIS DIAGRAM ...
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Figure 14-7. G.802 Timing NOTE 1: RCHBLK OR TCHBLK IS PROGRAMMED TO PULSE HIGH DURING TIME SLOTS 25, AND DURING BIT 1 OF TIME SLOT 26 ...
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Figure 14-8. Synchronization Flowchart ...
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Figure 14-9. Transmit Data Flow NOTE 1: TCLK MUST BE TIED TO RCLK (OR SYSCLK IF THE ELASTIC STORE IS ENABLED) AND TSYNC MUST BE TIED TO RSYNC FOR DATA TO BE PROPERLY SOURCED FROM RSER ...
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... Supply DS2153QN Table 15-2. Capacitance (T = +25°C) A PARAMETER Input Capacitance Output Capacitance Table 15-3. DC Characteristics = 5V ±5 0°C to +70°C for DS2153Q DS2153QN.) PARAMETER Supply Current at 5V Input Leakage Output Leakage Output Current (2.4V) Output Current (0.4V) NOTES: 1) Applies to RVDD, TVDD, and DVDD. 2) TCLK =2.048MHz. ...
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... AC CHARACTERISTICS Table 16-1. AC Characteristics—Parallel Port = 5V ±5 0°C to +70°C for DS2153Q DS2153QN.) (See Figure 16-1, PARAMETER Cycle Time Pulse Width, DS Low or RD High Pulse Width, DS High or RD Low Input Rise/Fall Times R/ Hold Time W R/ Setup Time before DS W High ...
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Figure 16-1. Intel Bus Read AC Timing Figure 16-2. Intel Bus Write AC Timing ...
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Figure 16-3. Motorola Bus AC Timing ...
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... Table 16-2. AC Characteristics—Receive Side = 5V ±5 0°C to +70°C for DS2153Q DS2153QN.) (See Figure 16-4.) PARAMETER ACLKI/RCLK Period RCLK Pulse Width RCLK Pulse Width SYSCLK Period SYSCLK Pulse Width RSYNC Setup to SYSCLK Falling RSYNC Pulse Width SYSCLK Rise/Fall Times Delay RCLK or SYSCLK to ...
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Figure 16-4. Receive Side AC Timing NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR1.5 = 0). NOTE 2: RSYNC IS IN THE INPUT MODE (RCR1.5 = 1). NOTE 3: RLCLK AND RLINK ONLY HAVE A TIMING RELATIONSHIP TO RCLK. ...
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... Table 16-3. AC Characteristics—Transmit Side = 5V ±5 0°C to +70°C for DS2153Q DS2153QN.) (See Figure 16-5.) PARAMETER TCLK Period TCLK Pulse Width TSER and TLINK Set up to TCLK Falling TSER and TLINK Hold from TCLK Falling TSYNC Set up to TCLK Falling TSYNC Pulse Width ...
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Figure 16-5. Transmit Side AC Timing NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR1.0 = 1). NOTE 2: TSYNC IS IN THE INPUT MODE (TCR1.0 = 0). NOTE 3: NO TIMING RELATIONSHIP BETWEEN TSYNC AND TLCLK/TLINK IS IMPLIED. NOTE ...
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