PCU9655PW,518 NXP Semiconductors, PCU9655PW,518 Datasheet
PCU9655PW,518
Specifications of PCU9655PW,518
Related parts for PCU9655PW,518
PCU9655PW,518 Summary of contents
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PCU9655 16-channel UFm 5 MHz bus 100 LED driver Rev. 2 — 2 October 2012 1. General description The PCU9655 is a UFm I switch dimming and blinking 100 mA Red/Green/Blue/Amber (RGBA) LEDs. Each LED output has ...
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... NXP Semiconductors 2. Features and benefits 16 LED drivers. Each output programmable at: Off On Programmable LED brightness Programmable group dimming/blinking mixed with individual LED brightness Programmable LED output enable delay to reduce EMI and surge currents 16 output channels can sink up to 100 mA, tolerate when OFF ...
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... NXP Semiconductors 3. Applications Amusement products RGB or RGBA LED drivers LED status information LED displays LCD backlights Keypad backlights for cellular phones or handheld devices 4. Ordering information Table 1. Ordering information Type number Topside mark PCU9655PW PCU9655 PCU9655PW1 PU96551 5 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning LED0 LED1 LED2 LED3 V SS LED4 LED5 LED6 LED7 a. PCU9655PW Fig 2. 6.2 Pin description Table 2. Symbol LED0 LED1 LED2 LED3 V SS LED4 LED5 LED6 LED7 LED8 LED9 LED10 PCU9655 Product data sheet 16-channel UFm 5 MHz bus 100 LED driver ...
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... NXP Semiconductors Table 2. Symbol LED11 LED12 LED13 LED14 LED15 RESET n.c. USCL USDA V DD [1] In order to obtain the best system level ESD performance, a standard pull-up resistor (10 k typical) is required for any address pin connecting to V performance, please refer to application notes AN10897 and AN11131. ...
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... NXP Semiconductors Fig 3. The last bit of the address byte defines the operation to be performed. Only writes to PCU9655 are supported, therefore the last bit is set to 0. 7.1.2 LED All Call UFm I • Default power-up value (ALLCALLADR register): A0h or 1010 000X • Programmable through I • ...
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... NXP Semiconductors This AIF bit along with the MODE1 register bit 5 and bit 6 provide the Auto-Increment feature. Fig 4. When the Auto-Increment Flag is set (AIF = 1), the seven low-order bits of the Control register are automatically incremented after a write. This allows the user to program the registers sequentially ...
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... NXP Semiconductors When the Control register is written, the register entry point determined by D[6:0] is the first register that will be addressed (write operation), and can be anywhere between 00h and 41h (as defined in rollover value at which the register increment stops and goes to the next one is determined by AIF, AI1 and AI0 ...
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... NXP Semiconductors [1] Table 4. Register summary Register number (hexadecimal) 15h 16h 17h 18h 19h 1Ah to 39h - - - 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h to 7Fh ...
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... NXP Semiconductors 7.3.1 MODE1 — Mode register 1 Table 5. MODE1 - Mode register 1 (address 00h) bit description Legend: * default value. Bit Symbol Access 7 AIF - 6 AI1 W only 5 AI0 W only 4 SLEEP W only 3 SUB1 W only 2 SUB2 W only 1 SUB3 W only 0 ALLCALL W only It takes 500 s max. for the oscillator and running once SLEEP bit has been set to logic 0. Timings on LEDn outputs are not [1] guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 ...
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... NXP Semiconductors 7.3.3 LEDOUT0 to LEDOUT3, LED driver output state Table 7. Legend: * default value. Address 02h 03h 04h 05h LDRx = 00 — LED driver x is off (default power-up state). LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking not controlled). LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx register. LDRx = 11 — ...
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... NXP Semiconductors When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers define a global blinking pattern, where GRPFREQ contains the blinking period (from 16.8 s) and GRPPWM the duty cycle (ON/OFF ratio in %). duty cycle 7.3.5 GRPFREQ, group frequency Table 9. Legend: * default value. ...
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... NXP Semiconductors A 31.25 kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h (0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs programmed with LDRx = (LEDOUT0 to LEDOUT3 registers). ...
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... NXP Semiconductors channel 13 turns on at time 13 s channel 14 turns on at time 14 s channel 15 turns on at time 15 s 7.3.8 SUBADR[3:1] LED Sub Call UFm I Table 12. Legend: * default value. Address Register 3Bh 3Ch 3Dh Default power-up values are ACh, ACh, ACh. At power-up, SUBADR1 is enabled while SUBADR2 and SUBADR3 are disabled ...
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... NXP Semiconductors 7.3.12 PWMALL — brightness control for all LEDn outputs When programmed, the value in this register will be used for PWM duty cycle for all the LEDn outputs. Table 14. Legend: * default value. Address 42h Remark: Write to any of the PWM0 to PWM15 registers will overwrite the value in corresponding PWMn register ...
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... NXP Semiconductors 7.6 Software reset The Software Reset Call (SWRST Call) allows all the devices in the UFm I reset to the power-up state value through a specific formatted I The maximum wait time after software reset is 1 ms. The SWRST Call function is defined as the following START command is sent by the UFm I 2. The reserved General Call address ‘ ...
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... NXP Semiconductors 7.7 Individual brightness control with group dimming/blinking A 31.25 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control individually the brightness for each LED. On top of this signal, one of the following signals can be superimposed (this signal can be applied to the 16 LED outputs LED0 to LED15 because the count started at 0): • ...
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... NXP Semiconductors 8. Characteristics of the PCU9655 Ultra Fast-mode I The PCU9655 LED controller uses the new Ultra Fast-mode (UFm) I communicate with the UFm I Fast-mode Plus (Fm+) I line (USDA) and a serial clock line (USCL). The UFm is a unidirectional bus that is capable of higher frequency ( MHz). The UFm I receive-only mode ...
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... NXP Semiconductors 8.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see MASTER UFm TRANSMITTER Fig 9. ...
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... NXP Semiconductors 9. Bus transactions slave address START condition (1) See Table 4 for register definition. Fig 11. Write to a specific register slave address START condition W this bit always = 1 RESERVED3 register data (cont.) 1 this bit always = 1 ...
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START condition W register selection this bit is Auto-Increment on always = 1 PWM14 register data PWM15 register data (cont.) 1 this bit ...
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... NXP Semiconductors slave address sequence ( START condition 2 LED All Call I C address sequence ( START condition LEDOUT1 register (LED fully ON) (cont (1) In this example, several PCU9655s are used and the same sequence (A) (above) is sent to each of them. ...
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... NXP Semiconductors 10. Application design-in information V = 2 kΩ UFm MASTER USDA USCL I/O 10 kΩ (1) (1) A standard 10 k pull-up resistor is required to obtain the best system level ESD performance. Fig 15. Typical application PCU9655 Product data sheet 16-channel UFm 5 MHz bus 100 LED driver ...
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... NXP Semiconductors 10.1 Thermal considerations Since the PCU9655 device integrates 16 voltage switches, thermal considerations should be taken into account to prevent overheating, which can cause the device to go into thermal shutdown. In order to ensure that the device will not go into thermal shutdown when operating under certain application conditions, its junction temperature (T that is below the overtemperature threshold limit (125 ...
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... NXP Semiconductors It is important to mention that the value of the thermal resistance junction-to-ambient (R ) strongly depends on the PCB design. Therefore, the device pins should be th(j-a) attached to a big enough PCB copper area to ensure proper thermal dissipation (similar to JEDEC 51 standard). Several thermal vias should be used as well in a multi-layer PCB design to increase the effectiveness of the heat dissipation ...
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... NXP Semiconductors 13. Static characteristics Table 17. Static characteristics 5 amb Symbol Parameter Supply V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR V power-down reset voltage PDR Input USCL; input USDA V LOW-level input voltage IL V HIGH-level input voltage ...
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... NXP Semiconductors 14. Dynamic characteristics Table 18. Dynamic characteristics All the timing limits are valid within the operating supply voltage and ambient temperature range; V 5 +85 amb Symbol Parameter f USCL clock frequency USCL t bus free time between a STOP and START ...
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... NXP Semiconductors USDA t BUF t LOW USCL t HD;STA P S Fig 16. Definition of timing START protocol condition ( SU;STA LOW USCL t BUF USDA t HD;STA Rise and fall times refer Fig 17. UFm I C-bus timing diagram PCU9655 Product data sheet 16-channel UFm 5 MHz bus 100 LED driver ...
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... NXP Semiconductors 15. Test information Fig 18. Test circuitry for switching times PCU9655 Product data sheet 16-channel UFm 5 MHz bus 100 LED driver V PULSE GENERATOR R = Load resistor for LEDn Load capacitance includes jig and probe capacitance Termination resistance should be equal to the output impedance Z T All information provided in this document is subject to legal disclaimers ...
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... NXP Semiconductors 16. Package outline TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 17. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 18.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 20. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 19. Abbreviations Table 21. Acronym CDM DUT ESD FET HBM 2 I C-bus LED LCD LSB MSB NMOS PCB ...
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... NXP Semiconductors 20. References [1] AN10897, “A guide to designing for ESD and EMC” — NXP Semiconductors [2] AN11131, “How to improve system level ESD performance” — NXP Semiconductors 21. Revision history Table 22. Revision history Document ID Release date PCU9655 v.2 20121002 • Figure 2b: sub-title corrected from “PCU9665PW1” to “PCU9655PW1” ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... Product data sheet 16-channel UFm 5 MHz bus 100 LED driver own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 24. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 7.1 Device addresses . . . . . . . . . . . . . . . . . . . . . . . 5 2 7.1.1 Regular UFm I C-bus slave address . . . . . . . . 5 2 7.1.2 LED All Call UFm I C-bus address ...