MAX5980GTJ+T Maxim Integrated, MAX5980GTJ+T Datasheet

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MAX5980GTJ+T

Manufacturer Part Number
MAX5980GTJ+T
Description
Power Switch ICs - POE / LAN 0-16V Hot-Swap Controller
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX5980GTJ+T

Rohs
yes
Number Of Switches
Quad
Off Time (max)
0.1 ms
Operating Supply Voltage
32 V to 60 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Maximum Power Dissipation
2758.6 mW
Minimum Operating Temperature
- 40 C
Operating Supply Current
5 mA
19-5568; Rev 1; 9/11
The MAX5980 is a quad, power-sourcing equipment
(PSE) power controller designed for use in IEEE
802.3at/af-compliant PSE. This device provides powered
device (PD) discovery, classification, current limit, and
load disconnect detection. The device supports both
fully automatic operation and software programmability.
The device also supports new 2-event classification and
Class 5 for detection and classification of high-power
PDs. The device supports single-supply operation, pro-
vides up
provides high-capacitance detection for legacy PDs.
The device features an I
interface, and is fully software configurable and pro-
grammable. The device provides instantaneous readout
of port current and voltage through the I
device’s extensive programmability enhances system
flexibility, enables field diagnosis, and allows for uses in
other, nonstandard applications.
The device is available in a space-saving, 32-pin TQFN
(5mm x 5mm) power package and is rated for the auto-
motive (-40NC to +105NC) temperature range.
IEEE is a registered service mark of the Institute of Electrical and
Electronics Engineers, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
to 70W
EN
to each port (Class 5 enabled), and still
-54V
_______________________________________________________________ Maxim Integrated Products 1
MIDSPAN
EN_CL5
AGND
AUTO
V
EN
DD
A0
A1
A2
A3
General Description
Quad, IEEE 802.3at/af PSE Controller
2
C-compatible, 3-wire serial
-54V
2
MAX5980
C interface. The
®
for Power-over-Ethernet
S
S
S
S
S
S
S
S
S
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
MAX5980GTJ+
OUT1
GATE1
OUT2
GATE2
OUT3
GATE3
OUT4
GATE4
IEEE 802.3at/af Compliant
0.25I Current-Sensing Resistor
Up to 70W per Port for PSE Applications
9-Bit Port Current and Voltage Monitoring
I
Supports Single-Supply Operation
High-Capacitance Detection for Legacy Devices
Supports DC Load-Removal Detections
Space-Saving, 32-Pin TQFN (5mm x 5mm) Power
Package
2
C-Compatible, 3-Wire Serial Interface
PSE-ICM
Power-Sourcing Equipment (PSE)
Switches/Routers
Midspan Power Injectors
PART
Simplified Operating Circuit
-40NC to +105NC
TEMP RANGE
Ordering Information
OUTPUT
PORT 1
OUTPUT
PORT 2
OUTPUT
PORT 3
Applications
OUTPUT
PORT 4
PIN-PACKAGE
32 TQFN-EP*
Features

Related parts for MAX5980GTJ+T

MAX5980GTJ+T Summary of contents

Page 1

... EN EN AUTO MIDSPAN EN_CL5 _______________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. for Power-over-Ethernet IEEE 802.3at/af Compliant S ® 0.25I Current-Sensing Resistor 70W per Port for PSE Applications ...

Page 2

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet ABSOLUTE MAXIMUM RATINGS (Voltages referenced unless otherwise noted.) EE AGND ....................................................................-0.3V to +80V DGND, SVEE_ ......................................................-0.3V to +0.3V V ........................ -0.3V to the lower (V DD OUT_ ....................................................-0. ...

Page 3

Quad, IEEE 802.3at/af PSE Controller ELECTRICAL CHARACTERISTICS (continued 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, and default register settings. Currents are positive when entering ...

Page 4

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet ELECTRICAL CHARACTERISTICS (continued 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, and default register settings. Currents are positive ...

Page 5

Quad, IEEE 802.3at/af PSE Controller ELECTRICAL CHARACTERISTICS (continued 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, and default register settings. Currents are positive when entering ...

Page 6

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet ELECTRICAL CHARACTERISTICS (continued 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, and default register settings. Currents are positive ...

Page 7

Quad, IEEE 802.3at/af PSE Controller (V = 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, ENDPOINT mode, and default register settings with a Class 0 PD, unless ...

Page 8

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet (V = 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, ENDPOINT mode, and default register settings with a Class 0 ...

Page 9

Quad, IEEE 802.3at/af PSE Controller (V = 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, ENDPOINT mode, and default register settings with a Class 0 PD, unless ...

Page 10

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet (V = 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, ENDPOINT mode, and default register settings with a Class 0 ...

Page 11

Quad, IEEE 802.3at/af PSE Controller (V = 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, ENDPOINT mode, and default register settings with a Class 0 PD, unless ...

Page 12

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet TOP VIEW GATE1 OUT1 SVEE1 EN_CL5 AUTO MIDSPAN *CONNECT TO V PIN NAME 3-Wire Serial Interface Input Clock Line. Referenced to DGND. Connect to DGND if the I 1 SCL not used. Serial ...

Page 13

Quad, IEEE 802.3at/af PSE Controller PIN NAME Analog Low-Side Supply Input. Bypass with an external 100V, 0.1FF ceramic capacitor between AGND and V Digital High-Side Supply Output. Bypass with an external RC network; see the V 12 ...

Page 14

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet SCL SDAIN SDAOUT SERIAL PORT INTERFACE (SPI) AUTO MIDSPAN REGISTER FILE EN_CL5 A3–A0 INT CENTRAL LOGIC UNIT (CLU) AGND ANALOG INTERNAL DGND BIAS AND REFERENCES SUPPLY AND SUPPLIES MONITORS ...

Page 15

Quad, IEEE 802.3at/af PSE Controller Detailed Description The MAX5980 is a quad PSE power controller designed for use in IEEE 802.3at/af-compliant PSE. This device provides PD discovery, classification, current limit, and load disconnect detections. The device supports both fully automatic ...

Page 16

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Semiautomatic (Semi) Mode Enter semiautomatic mode by setting the port operating mode (R12h, Table 19) to [10]. When entering semi mode, the DET_EN_ and CLASS_EN_ bits retain their previous states. When the DET_EN_ ...

Page 17

Quad, IEEE 802.3at/af PSE Controller To prevent damage to non-PD devices, and to protect itself from an output short circuit, the device limits the current into OUT_ to less than 2mA (max) during PD detection. In midspan mode, after every ...

Page 18

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet 80ms 150ms t 0V -4V -9.1V -18V -54V OUT_ AGND Figure 1. Detection, Classification, and Port Power-Up Sequence 2-Event PD Classification If the result of the first classification event is ...

Page 19

Quad, IEEE 802.3at/af PSE Controller 80ms 150ms t DET(1) 0V -4V -9.1V -18V -54V OUT_ AGND Figure 2. Detection, 2-Event Classification, and Port Power-Up Sequence V exceeds V and decreases at a slower RSENSE_ CUT pace when ...

Page 20

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet SENSE_ EE CLASS 4 V SU_LIM 212.5mV CLASS 0 –3 V SU_LIM 106.25mV V TH_FB 35mV Figure 3. Foldback Current Characteristics Foldback Current During startup and normal operation, an internal ...

Page 21

Quad, IEEE 802.3at/af PSE Controller Undervoltage and Overvoltage Protection The device contains undervoltage and overvoltage pro- tection features, and the flag bits can be found in the Supply Event register (R0Ah and R0Bh, Table 12) and the Watchdog register (R42h, ...

Page 22

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet SDA/SDAIN t LOW SCL t HIGH t HD, STA t R START CONDITION Figure 5. Serial Interface Timing Details Table 3. Programmable Device Address Settings Device Address (AD0) The ...

Page 23

Quad, IEEE 802.3at/af PSE Controller START and STOP Conditions Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to ...

Page 24

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet The device has a 7-bit long slave address (Figure 9). The bit following the 7-bit slave address (bit eight) is the R/W bit, which is low for a write command and high for ...

Page 25

Quad, IEEE 802.3at/af PSE Controller CONTROL BYTE STORED ON STOP CONDITION ACKNOWLEDGE FROM THE MAX5980 S SLAVE ADDRESS R/W Figure 11. Write Format, Control, and Single Data Byte Written CONTROL BYTE STORED ON STOP CONDITION ACKNOWLEDGE FROM THE MAX5980 S ...

Page 26

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Operation with Multiple Masters When the device operates on a 3-wire interface with mul- tiple masters, a master reading the device should use repeated starts between the write that sets the device’s address ...

Page 27

Quad, IEEE 802.3at/af PSE Controller Table 5. Register Map Summary (continued) REGISTER ADDR TYPE BIT 7 NAME STATUS 0Ch Port 1 Status R — 0Dh Port 2 Status R — 0Eh Port 3 Status R — 0Fh Port 4 Status ...

Page 28

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Table 5. Register Map Summary (continued) REGISTER ADDR TYPE BIT 7 NAME MAXIM RESERVED 20h Reserved — — 21h Reserved — — 22h Reserved — — 23h Reserved — — 24h Reserved — ...

Page 29

Quad, IEEE 802.3at/af PSE Controller Table 5. Register Map Summary (continued) REGISTER ADDR TYPE BIT 7 NAME Developer 43h ID/Revision R/W DEV_ID[2] Number High-Power 44h R/W — Enable 45h Reserved —- — 46h Port 1 GPMD R/W — 47h Port ...

Page 30

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Register Map and Description The device contains a bank of volatile registers that store its settings and status. The device features an I compatible, 3-wire serial interface, allowing the registers to be fully ...

Page 31

Quad, IEEE 802.3at/af PSE Controller Interrupt Mask Register (R01h) The Interrupt Mask register (R01h, Table 7) contains mask bits that suppress the corresponding interrupt bits in register R00h (active-high). Setting mask bits low individually disables the corresponding interrupt signal. When ...

Page 32

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Detect Event Register (R04h/R05h) The Detect Event register (R04h/R05h, Table 9) records detection/classification events for the port. On power-up or after a reset condition, the Detect Event register is set to a default ...

Page 33

Quad, IEEE 802.3at/af PSE Controller Startup Event Register (R08h/R09h) The Startup Event register (R08h/R09h, Table 11) records port startup failure events and current-limit disconnect timeout events. On power-up or after a reset condition, the Fault Event register is set to ...

Page 34

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Status Registers (R0Ch–R11h) Port Status Registers (R0Ch–R0Fh) The Port Status registers (R0Ch–R0Fh, Table 13) record the results of the port detection and classification at the end of each phase in three encoded bits. ...

Page 35

Quad, IEEE 802.3at/af PSE Controller Power Status Register (R10h) The Power Status register (R10h, Table 16) records the current status of port power. On power-up or after a reset condition, the port is initially unpowered and the Power Status register ...

Page 36

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Configuration Registers (R12h–R17h) Operating Mode Register (R12h) The Operating Mode register in the device (R12h, Table 19) contains 2 bits per port that set the port mode of operation. Table 20 details how ...

Page 37

Quad, IEEE 802.3at/af PSE Controller Detection and Classification Enable Register (R14h) The Detection and Classification Enable register (R14h, Table 22) is used to enable detection and classification routines for the ports power-up or after a reset con- dition, ...

Page 38

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Miscellaneous Configuration 1 Register (R17h) The Miscellaneous Configuration 1 register (R17h, Table 24) is used for several functions that do not cleanly fit within one of the other configuration catego- ries ...

Page 39

Quad, IEEE 802.3at/af PSE Controller Pushbutton Registers (R18h–R1Ah) Detection/Classification Pushbutton Register (R18h) The Detection/Classification Pushbutton register (R18h, Table 25) is used as a pushbutton to set the corre- sponding bits in the Detection and Classification Enable register (R14h, Table 22). ...

Page 40

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet General Registers (R1Bh–R1Fh) The ID register (R1Bh, Table 28) keeps track of the device ID number and revision. The device’s ID code is stored in ID_CODE[4:0] (R1Bh[7:3]) and is 11010. Contact the factory ...

Page 41

Quad, IEEE 802.3at/af PSE Controller TLIM Programming Registers (R1Eh and R1Fh) The TLIM Programming registers (R1Eh/R1Fh, Table 30) are used to adjust the t current-limit timeout duration. LIM On a power-up or after a reset condition, this register is set ...

Page 42

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Current/Voltage Readout Registers Port Current Registers (R30h, R31h, R34h, R35h, R38h, R39h, and R3Ch, R3Dh) The Port Current registers (Tables 32 and 33) provide port current readout when a port is powered on. ...

Page 43

Quad, IEEE 802.3at/af PSE Controller Port Voltage Registers (R32h, R33h, R36h, R37h, R3Ah, R3Bh, R3Eh, and R3Fh) The Port Voltage registers (Tables 34 and 35) provide port voltage readout when a port is powered on power-up or after ...

Page 44

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Other Functions Registers (R00h, R01h) Reserved Registers (R40h, R45h, R4Ah, R4Fh, R54h, R59h, R5Ah, R5Bh, R5Ch, R5Dh, R5Eh, R5Fh) These registers are at this time reserved. Writing to these registers will have no ...

Page 45

Quad, IEEE 802.3at/af PSE Controller High-Power Enable Register (R44h) The High-Power Enable register (R44h, Table 38) is used to enable the high-power features on the ports. On power-up or after a reset condition, if AUTO = 1, this register is ...

Page 46

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Port Current-Limit Register (R48h, R4Dh, R52h, and R57h) The Port Current-Limit registers (Table 41) are used to set the current-limit SENSE_ voltage threshold for the corre- sponding port power-up or after ...

Page 47

Quad, IEEE 802.3at/af PSE Controller ___________Applications Information Layout Procedure Careful PCB layout is critical to achieve high efficiency and low EMI. Follow these layout guidelines for optimal performance: 1) Place the high-frequency input bypass capacitor (0.1FF ceramic capacitor from AGND ...

Page 48

Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet 50I CURRENT SHARING 33nF WITH OTHER MAX5980 200I 3.3V 200I HPCL063L GND OPTIONAL BUFFER 200I HPCL063L OPTIONAL BUFFER SDA -54V 200I HPCL063L 3kI OPTIONAL BUFFER SCL -54V INTERNAL PULLUP TO V (AUTO MODE ...

Page 49

... Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © ...

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