MCIMX6U5DVM10AB Freescale Semiconductor, MCIMX6U5DVM10AB Datasheet
MCIMX6U5DVM10AB
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MCIMX6U5DVM10AB Summary of contents
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... WLAN, Bluetooth™, GPS, hard drive, displays, and camera sensors. The i.MX 6Solo/6DualLite processors are specifically useful for applications such as: • Web and multimedia tablets © 2012 Freescale Semiconductor, Inc. All rights reserved. Document Number: IMX6SDLCEC Rev. 1, 11/2012 MCIMX6SxExxxxxB MCIMX6SxDxxxxxB MCIMX6UxExxxxxB ...
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... Advanced security—The processors deliver hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption, secure boot, and secure i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev ® ES 2.0 3D graphics accelerator with a shader and a 2D graphics 2 S serial audio, and PCIe-II). Freescale Semiconductor ...
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... The latest part numbers are available on the web page freescale.com/imx6series. If the desired part number is not listed in the web page freescale.com/imx6series or contact a Freescale representative. Solo/DualLite Part Number CPU MCIMX6U8DVM10AB i.MX 6DualLite With VPU, GPU, EPD, no MCIMX6U5DVM10AB i.MX 6DualLite With VPU, GPU, no EPD, no MCIMX6U5EVM10AB i.MX 6DualLite With VPU, GPU, no EPD, no MCIMX6S8DVM10AB i.MX 6Solo MCIMX6S5DVM10AB i.MX 6Solo MCIMX6S5EVM10AB i ...
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... Extended Consumer: - 105C E Industrial: -40 to +105C C Automotive: - 125C Silicon Rev B Rev 1.1 B Fusing % Real Co dec o ff & no HDCP o r DTCP A Real Co dec o ff with HDCP on C Frequency $$ 2 800 MHz GHz 10 Package Type ROHS MAPBGA 21x21 0.8mm VM Freescale Semiconductor ...
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... One Parallel 24-bit display port 225 Mpixels/sec (for example, WUXGA dual HD1080 and WXGA at 60 Hz) — LVDS serial ports—One port up to 165 Mpixels/sec or two ports MP/sec (for example, WUXGA at 60 Hz) each — HDMI 1.4 port i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Introduction Table 9, "Operating Ranges," on page 5 ...
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... The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx) due to internal bus throughput limitations. The actual measured performance in optimized environment 400 Mbps. For details, see the ERR004512 erratum in the i.MX 6Solo/6DualLite errata document (IMX6SDLCE). i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev Mbps Freescale Semiconductor ...
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... TZ policy. • A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements: SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Introduction 7 ...
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... Table 1, MIPI HDMI 1.4 Display Display DSI/MIPI E-INK EPDC Display PxP MMC/SD AP Peripherals eMMC/eSD uSDHC (4) MMC/SD SDXC AUDMUX 2 I C(4) PWM (4) Modem IC OCOTP_CTRL IOMUXC KPP GPIO Keypad CAN(2) 1-Gbps ENET HSI/MIPI Ethernet 10/100/1000 USB OTG + Mbps 3 HS Ports USB OTG Freescale Semiconductor ...
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... Rate Converter AUDMUX Digital Audio Mux BCH40 Binary-BCH ECC Processor i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor NOTE Table 2. i.MX 6Solo/6DualLite Modules List Subsystem ARM The ARM Core Platform includes 1x (Solo) Cortex-A9 core for i.MX 6Solo and 2x (Dual) Cortex-A9 cores for i ...
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... The MIPI DSI IP provides DSI standard display port Peripherals interface. The DSI interface support 80 Mbps to 1 Gbps speed per data lane. Connectivity Full-duplex enhanced Synchronous Serial Interface, Peripherals with data rate Mbit/ configurable to support Master/Slave modes, four chip selects to support multiple peripherals. Brief Description Freescale Semiconductor ...
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... Enhanced Periodic EPIT-2 Interrupt Timer ESAI Enhanced Serial Audio Interface i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Subsystem Connectivity The Ethernet Media Access Controller (MAC) is Peripherals designed to support 10/100/1000 Mbps Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media ...
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... Electromagnetic interference (EMI) environment of a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module is a full implementation of the CAN protocol specification, Version 2.0 B, which supports both standard and extended message frames. Freescale Semiconductor ...
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... C-4 i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Subsystem Security Electrical Fuse Array. Enables to setup Boot Modes, Security Levels, Security Keys, and many other system parameters. The i.MX 6Solo/6DualLite processors consist of 512x8-bit fuse fox accessible through OCOTP_CTRL interface. System Control Used for general purpose input/output to external ICs ...
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... Each signal pair contains LVDS special differential pad (PadP, PadM). Connectivity DDR Controller has the following features: Peripherals • Supports 16/32-bit DDR3-800 (LV) or LPDDR2-800 in i.MX 6Solo • Supports 16/32/64-bit DDR3-800 (LV) or LPDDR2-800 in i.MX 6DualLite • Supports 2x32 LPDDR2-800 in i.MX 6DualLite • Supports GByte DDR memory space Brief Description Freescale Semiconductor ...
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... Boot ROM 96KB ROMCP ROM Controller with Patch i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Subsystem Security The On-Chip OTP controller (OCOTP_CTRL) provides an interface for reading, programming, and/or overriding identification and control information stored in on-chip fuse elements. The module supports electrically-programmable poly fuses (eFUSEs) ...
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... A standard audio file transfer format, developed jointly Peripherals by the Sony and Phillips corporations. Has Transmitter and Receiver functionality. Security Secure Non-Volatile Storage, including Secure Real Time Clock, Security State Machine, Master Key Control, and Violation/Tamper Detection and reporting. Brief Description Freescale Semiconductor ...
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... USBOH3 USB 2.0 High Speed OTG and 3x HS Hosts VDOA VDOA i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Subsystem Connectivity The SSI is a full-duplex synchronous interface, which is Peripherals used on the AP to provide connectivity with off-chip audio peripherals. The SSI supports a wide variety of ...
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... Support 16-bit (in muxed IO mode only) NOR-Flash memories, at slow frequency • Multiple chip selects Clocks, Resets, and The XTALOSC module enables connectivity to external Power Control crystal oscillator device typical application use-case used for 24 MHz oscillator to provide USB required frequency. Brief Description Freescale Semiconductor ...
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... If this clock is used as a reference for USB and PCIe, then there are strict frequency tolerance and jitter requirements. See OSC24M chapter and relevant interface specifications chapters for details. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Section 6, “Package Information and Contact Table 3. Special Signal Considerations ...
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... The user must either float this signal or tie it to GND. The impedance calibration process requires connection of reference resistor 200 Ω 1% precision PCIE_REXT resistor on PCIE_REXT pad to ground. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev Remarks Table 4. Use of external resistors is unnecessary. However, Freescale Semiconductor ...
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... RGMII_RXC, RGMII_TD0, RGMII_TD1, RGMII_TD2, RGMII_TD3, RGMII_TX_CTL, RGMII_TXC USB USB_H1_DN, USB_H1_DP, USB_H1_VBUS, USB_OTG_CHD_B, USB_OTG_DN, USB_OTG_DP, USB_OTG_VBUS 1 In this case, the BSR chain will not work. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Remarks Table 4. JTAG Controller Interface Summary I/O Type Input Input Input 3-state output ...
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... Supplies denoted as I/O supply VDD_SNVS_IN VDDHIGH_IN VBUS USB_DP/USB_DN out Table 6 for a quick reference Topic appears … on page 22 on page 23 on page 24 on page 26 on page 27 on page 29 on page 30 on page 30 Min Max Unit -0.3 1.5 V -0.3 1.3 V -0.5 3.6 V -0.4 1.975 V -0.3 2.8 V -0.3 3.3 V -0.3 3.6 V — 5.25 V -0.3 3. -0.5 OVDD +0.3 V Freescale Semiconductor ...
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... Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Symbol V esd T STORAGE Table 8 ...
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... Should be supplied from the same supply as VDDHIGH_IN if the system does not require keeping real time and other data on OFF state. LPDDR2, DDR3-U DDR3 DDR3_L 1.15 V – 1. HSIC 1.2 V mode 1.43 V – 1. RMGII 1.5 V mode 1.70 V – 1. RMGII 1.8 V mode 2.25 V – 2.625 V in RMGII 2.5 V mode Freescale Semiconductor ...
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... This supply also powers the pre-drivers of the DDR IO pins, hence, it must be always provided, even when LVDS is not used Table 10 shows on-chip LDO regulators that can supply on-chip loads. Table 10. On-Chip LDOs Voltage Source VDDHIGH_CAP i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 9. Operating Ranges (continued) 1 Min Typ Max Unit 1 ...
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... Applications Processors for Consumer Products, Rev and their On-Chip Loads (continued) Load HDMI_VP Board-level connection to VDDSOC_CAP PCIE_VP PCIE_VPTX Table 11. External Input Clock Frequency Symbol Min f — 32.768 ckil f xtal Comment 2 3 Typ Max Unit 3 /32.0 — kHz 24 MHz Freescale Semiconductor ...
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... Power Line VDDARM_IN VDDSOC_IN VDDHIGH_IN VDD_SNVS_IN USB_OTG_VBUS/USB_H1_VBUS (LDO 3P0) i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 11 are required for use with Freescale BSPs to ensure precise time Table 12 represent a use case designed specifically to show the Table 12. Maximal Supply Currents Conditions ...
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... Use maximal IO equation N=24 Use maximal IO equation N=20 Use maximal IO equation N=53 Use maximal IO equation N=6 Use maximal IO equation N=12 Use maximal IO equation N=6 Use maximal IO equation N=6 Use maximal IO equation N=11 Use maximal IO equation N=26 Use maximal IO equation MISC — 1 Unit 4 — Freescale Semiconductor ...
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... XTAL and bandgap are disabled 1 The typical values shown here are for information only and are not guaranteed. These values are average values measured on a typical wafer at 25°C. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Test Conditions VDDARM_IN (1.4V) VDDSOC_IN (1.4V) VDDHIGH_IN (3.0V) Total VDDARM_IN (1 ...
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... Test Conditions Supply 5G Operations PCIE_VP (1.1 V) PCIE_VPTX (1.1 V) PCIE_VPH (2.5 V) 2.5G Operations PCIE_VP (1.1 V) PCIE_VPTX (1.1 V) PCIE_VPH (2 Operations PCIE_VP (1.1 V) PCIE_VPTX (1.1 V) PCIE_VPH (2.5 V) 2.5G Operations PCIE_VP (1.1 V) PCIE_VPTX (1.1 V) PCIE_VPH (2.5 V) PCIE_VP (1.1 V) PCIE_VPTX (1.1 V) PCIE_VPH (2.5 V) PCIE_VP (1.1 V) PCIE_VPTX (1.1 V) PCIE_VPH (2.5 V) NVCC_PLL_OUT (1.1 V) <0.5 μA Max Current Unit 2 2 2.4 12 1.3 mA 0.18 0.36 Freescale Semiconductor ...
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... If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other supply is switched on. • If VDDARM_IN and VDDSOC_IN are connected to different external supply sources, then the following restrictions apply: i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 16. HDMI PHY Current Drain Supply HDMI_VPH HDMI_VP HDMI_VPH ...
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... There are three digital LDO regulators (“Digital”, because of the logic loads that they drive, not because of their construction). The advantages of the regulators are to reduce the input supply variation because of i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev NOTE NOTE NOTE Section 6, “Package Information NOTE Freescale Semiconductor ...
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... Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed. Active-pull-down can also be enabled for systems requiring this feature. An alternate self-biased low-precision weak-regulator is included that can be i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Electrical Characteristics 33 ...
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... Table 18. 528 MHz PLL’s Electrical Parameters Parameter Clock output range Reference clock Lock time i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev Value 650 MHz ~1.3 GHz 24 MHz <11250 reference cycles Value 528 MHz PLL output 24 MHz <11250 reference cycles Freescale Semiconductor ...
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... It also implements a power mux such that it can be powered from either backup battery (VDD_SNVS_IN) or VDDHIGH_IN such as the oscillator consumes i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 21. ARM PLL’s Electrical Parameters Electrical Characteristics ...
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... PCB on either side of the quartz. A higher Cload will decrease oscillation margin, but increases current oscillating through the crystal. 50 kΩ 100 kΩ Equivalent series resistance of the crystal. Choosing a crystal with a higher value will decrease the oscillating margin. Comments Freescale Semiconductor ...
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... Table 9, unless otherwise noted. Parameter 1 High-level output voltage 1 Low-level output voltage 1,2 High-Level input voltagev i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor NOTE Table 23 Table 23. GPIO DC Parameters Symbol Test Conditions GPIO DC Electrical Characteristics V Ioh= -0.1mA OH (ipp_dse=001,010) Ioh= -1mA ...
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... Symbol Test Conditions VOH Ioh= -0.1mA VOL Iol= 0.1mA Vref 0 0.3*OVD V D 250 mV 250 mV 0.5*OVD mV D 0.5*OVD mV D 212 100 105 175 kΩ 1 Min Max Unit 0.9*OVDD 0.1*OVDD 0.49*OVDD 0.51*OVDD Freescale Semiconductor ...
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... Low-level output voltage Input Reference Voltage DC High-Level input voltage DC Low-Level input voltage DifferentialInput Logic High DifferentialInput Logic Low Termination Voltage Pull-up/Pull-down Impedance Mismatch Mmpupd i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Symbol Test Conditions Vih_DC Vil_DC Vih_diff Vil_diff Mmpupd Rres ...
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... From Output Test Point Under Test CL CL includes package, probe and fixture capacitance Figure 4. Load Circuit for Output Min Max 10 105 165 -2.9 2.9 Min Typ Max 250 350 450 1.25 1.375 1.6 0.9 1.025 1.25 1.125 1.2 1.375 Figure 4 and Freescale Semiconductor Unit Ω kΩ μA Unit ...
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... Output Pad Transition Times, rise/fall (Low Drive. ipp_dse=001) 1 Input Transition Times 1 Hysteresis mode is recommended for inputs with transition times greater than 25 ns. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor 80% 20% tr Figure 5. Output Transition Time Waveform Symbol Test Condition tr, tf ...
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... Vix(ac) Relative to Vref Vpeak — 1 Min Max Vref + 0.22 OVDD 0 Vref - 0.22 0.44 — — 0.44 -0.12 0.12 — 0.35 — 0.3 1.5 3.5 1 2.5 — 0.1 1 Min Typ Max Vref + 0.175 — OVDD 0 — Vref - 0.175 0.35 — — Vref - 0.15 — Vref + 0.15 — — 0.4 Freescale Semiconductor Unit V-ns V/ns ns Unit ...
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... AC parameters for LVDS I/O. Parameter 1 Differential pulse skew 2 Transition Low to High Time 2 Transition High to Low Time Operating Frequency Offset voltage imbalance i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Symbol Test Condition Varea 400 MHz tsr Driver impedance = 34 Ω t clk = 400 MHz SKD Figure Table 31 ...
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... Ztl attached to I/O pad and incident wave launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to OVDD. Output driver impedance is calculated from this voltage divider (see i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev NOTE Figure 7). Freescale Semiconductor ...
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... U,(V) OVDD Vref1 Vref 0 Vovdd - Vref1 Rpu = Rpd = Vovdd - Vref2 Figure 7. Impedance Matching Load for Measurement i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor OVDD PMOS (Rpu) Ztl Ω inches pad NMOS (Rpd) OVSS Vref2 × Ztl Vref1 Vref2 × Ztl ...
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... Table 34. DDR I/O Output Buffer Impedance Test Conditions DSE(Drive NVCC_DRAM=1.5 V Strength) (DDR3) DDR_SEL=11 Typ Value Unit 260 130 90 Ω Typ Value Unit 150 75 50 Ω Typical Unit NVCC_DRAM=1.2 V (LPDDR2) DDR_SEL=10 Hi-Z Hi-Z 240 240 120 120 Freescale Semiconductor Ω ...
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... Duration of POR_B to be qualified as valid (input slope = 5 ns) 4.9.2 WDOG Reset Timing Parameters Figure 9 shows the WDOG reset timing and WDOG_B (Output) i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 35 lists the timing parameters. CC1 Figure 8. Reset Timing Diagram Table 35. Reset Timing Parameters Parameter Table 36 lists the timing parameters ...
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... Data Sheet Nomenclature, Reference Manual External Signals and Pin Multiplexing Chapter, and IOMUXC Controller Chapter Nomenclature EIM_BCLK EIM_CSx EIM_RW EIM_OE EIM_EBx EIM_LBA EIM_A[25:16], EIM_DA[15:0] EIM_DAx (Addr/Data muxed mode) EIM_NFC_D (Data bus shared with NAND Flash) EIM_Dx (dedicated data bus) EIM_WAIT Min Max Unit 1 — RTC_XTALI cycle Freescale Semiconductor ...
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... EIM_EB2 D[31:24], — — EIM_EB3 1 For more information on configuration ports mentioned in this table, see the i.MX 6Solo/6DualLite reference manual. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 38. EIM Internal Module Multiplexing Non Multiplexed Address/Data Mode 16 Bit MUM = 0, MUM = 0, MUM = 0, DSZ = 110 ...
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... EIM module. All EIM output control WE2 ... WE1 WE4 WE6 WE8 WE10 WE12 WE14 WE16 Figure 10. EIM Outputs Timing Diagram WE18 WE19 WE20 WE21 Figure 11. EIM Inputs Timing Diagram WE3 WE5 WE7 WE9 WE11 WE13 WE15 WE17 Freescale Semiconductor ...
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... Output Data Valid 1.25 WE17 Clock rise to 0 Output Data 1.25 Invalid WE18 Input Data setup 2 time to Clock rise i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 39. EIM Bus Timing Parameters BCD = 0 BCD = 1 Max Min Max — — 0 — ...
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... Min Max — 2 — — 4 — — 2 — WE4 Address v1 WE6 WE14 WE15 WE10 WE12 WE18 1 BCD = 2 BCD = 3 Min Max Min Max — — — — — — — — — — — — WE5 WE7 WE11 WE13 D(v1) WE19 Freescale Semiconductor ...
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... ADV_B OE_B BEy_B Figure 14. Muxed Address/Data (A/D) Mode, Synchronous Write Access, WSC=6,ADVA=0, ADVN=1, and In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the data bus. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor WE4 Address V1 WE6 WE8 WE14 WE15 WE12 ...
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... Manual (IMX6SDLRM) for the EIM programming model. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev WE4 WE5 Address V1 WE6 WE15 WE10 WE12 Table 40 help you determine timing parameters relative to the chip WE19 Data WE18 WE7 WE11 WE13 Figure 16 through Freescale Semiconductor ...
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... Figure 16. Asynchronous Memory Read Access (RWSC = 5) INT_CLK MAXCSO CSx_B ADDR/ M_DATA WE_B ADV_B OE_B BEy_B MAXCO Figure 17. Asynchronous A/D Muxed Read Access (RWSC = 5) i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor start of access WE31 Address V1 WE39 WE35 WE37 D(V1) WE43 MAXDI start of access ...
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... BEy_B Figure 19. Asynchronous A/D Muxed Write Access i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev WE31 Address V1 WE33 WE39 WE45 D(V1) WE41 WE31 D(V1) Addr. V1 WE32A WE33 WE40A WE39 WE45 WE32 Next Address WE34 WE40 WE46 WE42 WE41 WE42 WE34 WE46 WE42 Freescale Semiconductor ...
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... OE_B BEy_B DATA[7:0] DTACK CSx_B ADDR Last Valid Address WE_B ADV_B OE_B BEy_B DATA DTACK i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor WE31 Address V1 WE39 WE35 WE37 D(V1) WE43 WE47 Figure 20. DTACK Read Access (DAP=0) WE31 Address V1 WE33 WE39 WE45 ...
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... RCSN) — (RBEA - RCSA) — (RBEN- RCSN) — (ADVA - CSA) — CSN 3 + (ADVN + ADVA + 1 - CSA) — WCSA — (WADVN + WADVA + ADH + 1 - WCSA) — CSN — — — — — — Freescale Semiconductor ...
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... In this table, ADVN means WADVN when write operation or RADVN when read operation this table, ADVA means WADVA when write operation or RADVA when read operation. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Determination by Synchronous measured 1 parameters MAXCO - MAXCSO + MAXDI ...
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... Applications Processors for Consumer Products, Rev DDR4 DDR5 DDR4 DDR5 DDR4 DDR7 COL/BA Symbol Table DDR1 DDR2 CK = 400 MHz Unit Min Max 0.47 0. 0.47 0. 800 — ps 580 — ps 800 — ps 580 — ps Freescale Semiconductor 41. ...
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... To receive the reported setup and hold values, write calibration should be performed in order to locate the DQS in the middle of DQ window. 2 All measurements are in reference to Vref level. 3 Measurements were done using balanced load and 25 Ω resistor from outputs to VDD_REF. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor DDR22 DDR23 DDR18 DDR17 Data Data ...
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... Measurements were done using balanced load and 25 Ω resistor from outputs to VDD_REF. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev DATA DATA DATA DATA DDR26 Figure 24. DDR3/DDR3L Read Cycle Table 43. DDR3/DDR3L Read Cycle Parameter DATA DATA DATA DATA CK = 400 MHz Symbol Min Max — 450 — Freescale Semiconductor Unit ps ...
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... LP6 CKE hold time 1 All measurements are in reference to Vref level. 2 Measurements were done using balanced load and 25 Ω resistor from outputs to VDD_REF. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor LP4 LP6 LP3 LP3 LP4 LP4 Table 44. LPDDR2 Timing Parameter ...
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... LP17 LP18 Figure 26. LPDDR2 Write Cycle Table 45. LPDDR2 Write Cycle Parameter Table LP18 Data Data Data Data LP18 CK = 400 MHz Symbol Min Max t 375 — 375 — -0.25 +0.25 DQSS t 0.4 - DQSH t 0.4 - DQSL Freescale Semiconductor 45. Unit ps ps tCK tCK tCK ...
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... GPMI signals at the module level for different operations under asynchronous mode. Table 47 describes the timing parameters (NF1–NF17) that are shown in the figures. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor DATA DATA DATA DATA LP26 Figure 27 ...
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... Figure 28. Command Latch Cycle Timing Diagram CLE CEn WE ALE IO[7:0] Figure 29. Address Latch Cycle Timing Diagram i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev NF2 NF1 NF3 NF5 NF6 NF7 NF8 NF9 Command NF1 NF3 NF4 NF10 NF11 NF5 NF7 NF6 NF8 NF9 Address NF4 Freescale Semiconductor ...
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... Table 47. Asynchronous Mode Timing Parameters ID Parameter NF1 CLE setup time NF2 CLE hold time NF3 CEn setup time NF4 CE hold time i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor NF1 NF3 NF10 NF11 NF5 NF6 NF8 NF9 Data to NF NF14 NF15 ...
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... tDSR N/A tDHR N/A 1 (continued) Example Timing for ≈ 100 GPMI Clock MHz Unit Min. Max — — — — — — — — — — ns (Figure 30). Freescale Semiconductor ...
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... CE_N CLE ALE CLK W/R# DQS DQS output enable DQ[7:0] DQ[7:0] Output enable Figure 32. Source Synchronous Mode Command and Address Timing Diagram i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor NF20 NF21 NF20 CMD ADD NF23 Electrical Characteristics NF19 NF21 NF22 ADD NF24 69 ...
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... Electrical Characteristics NF18 CE_N CLE ALE CLK W/R# DQS DQS output enable DQ[7:0] DQ[7:0] Output enable Figure 33. Source Synchronous Mode Data Write Timing Diagram i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev NF25 NF23 NF25 NF22 NF27 NF27 NF19 NF26 NF24 NF27 Freescale Semiconductor ...
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... W/R# DQS DQS output enable DQ[7:0] DQ[7:0] Output enable Figure 34. Source Synchronous Mode Data Read Timing Diagram DQS DQ[7:0] i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor NF25 NF22 tDVW D0 D1 tDQSQ tQHS Figure 35. DQS/DQ Read Valid Window Electrical Characteristics NF19 NF26 NF24 NF25 ...
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... PRE_DELAY x tCK tPOST POST_DELAY x tCK tCALS 0.5 x tCK tCALH 0.5 x tCK tDQSS tCK Figure 35 shows the timing diagram of DQS/DQ read valid NOTE Section 4.10.1, “Asynchronous for details. 1 Timing Unit Max. — ns — ns — ns — — ns — ns — ns — ns — ns Freescale Semiconductor ...
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... Read and Write Timing Figure 36. Samsung Toggle Mode Data Write Timing i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Electrical Characteristics 73 ...
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... NF21 Command/address DQ hold time NF22 clock period i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev Timing T = GPMI Clock Cycle Symbol Min. tCE CE_DELAY x tCK tCH 0.5 x tCK tCAS 0.5 x tCK tCAH 0.5 x tCK tCK 7.5 Unit Max. — ns — ns — ns — Freescale Semiconductor ...
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... ECSPI Timing Parameters This section describes the timing parameters of the ECSPI blocks. The ECSPI have separate timing parameters for master and slave modes. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor T = GPMI Clock Cycle Symbol Min. tPRE (PRE_DELAY+1) x tCK ...
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... Hmiso t SDRY lists the ECSPI master mode timing CS5 CS6 CS4 Min Max 43 — 15 21.5 — 7 — — Half SCLK period — Half SCLK period - 4 — Half SCLK period - 2 — — 0 — 5 — Freescale Semiconductor Unit ...
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... SSx Lead Time (CS setup time) CS6 SSx Lag Time (CS hold time) CS7 MOSI Setup Time CS8 MOSI Hold Time CS9 MISO Propagation Delay (C i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 51 lists the ECSPI slave mode timing CS2 CS2 Symbol t clk t SW ...
Page 78
... Freescale Semiconductor 3 Unit ...
Page 79
... Periodically sampled and not 100% tested. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor 1,2 Symbol Expression 5 — ...
Page 80
... Electrical Characteristics 63 SCKT (Input/Output) FST (Bit) Out FST (Word) Out Data Out FST (Bit) In FST (Word) In i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev First Bit Figure 40. ESAI Transmitter Timing 83 87 Last Bit 91 Freescale Semiconductor ...
Page 81
... SCKR (Input/Output) FSR (Bit) Out FSR (Word) Out Data In FSR (Bit) In FSR (Word) In i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor First Bit Figure 41. ESAI Receiver Timing Electrical Characteristics 70 72 Last Bit 75 81 ...
Page 82
... DAT0 DAT1 ...... DAT7 Figure 42. SD/eMMC4.3 Timing Card Input Clock SD1 Symbols Min Max 400 25/ 20/ 100 400 — — — 3 TLH t — 3 THL t -6.6 3.6 OD Freescale Semiconductor AC Unit kHz MHz MHz kHz ...
Page 83
... Clock Frequency (EMMC4.4 DDR) SD1 Clock Frequency (SD3.0 DDR) uSDHC Output / Card Inputs CMD, DAT (Reference to CLK) SD2 uSDHC Output Delay i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor – 50 MHz. – 52 MHz. Table 54 lists the eMMC4.4 timing characteristics. Be aware ...
Page 84
... ISU t IH Table 55 lists the SDR50/SDR104 timing Figure 44. SDR50/SDR104 Timing Symbols Card Input Clock t CLK t 0.3 0.3 –1 ISU Min Max Unit 2.6 — ns 1.5 — ns Min Max Unit 4.8 — ns 0.7*t ns CLK CLK 0.7*t ns CLK CLK – 2.5 — ns Freescale Semiconductor ...
Page 85
... ENET_RX_ER, and ENET_RX_CLK) The receiver functions correctly ENET_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the ENET_RX_CLK frequency. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Symbols Min Max t 1.5 — ...
Page 86
... ENET_TX_CLK frequency. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev Table 56 describes the timing parameters (M1–M4) shown Table 56. MII Receive Signal Timing 1 M4 Min. Max. Unit 5 — — ns 35% 65% ENET_RX_CLK period 35% 65% ENET_RX_CLK period Freescale Semiconductor ...
Page 87
... Table 58. MII Asynchronous Inputs Signal Timing ID Characteristic 1 M9 ENET_CRS to ENET_COL minimum pulse width 1 ENET_COL has the same timing in 10-Mbit 7-wire interface mode. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 57 describes the timing parameters (M5–M8) shown Table 57. MII Transmit Signal Timing 1 Min. ...
Page 88
... ENET_TX_EN, ENET0_TXD[1:0], ENET0_RXD[1:0] and ENET_RX_ER. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev Table 59 describes the timing parameters (M10–M15) M14 M15 M10 M11 M12 M13 Min. 0 — 40% 40% Max. Unit — — ns — ns 60% ENET_MDC period 60% ENET_MDC period Freescale Semiconductor ...
Page 89
... Symbol 2 T Clock cycle duration cyc 3 T Data to clock output skew at transmitter skewT i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 60 describes the timing parameters (M16–M21) shown in the M16 M18 M19 M20 M21 Table 60. RMII Signal Timing Characteristic ...
Page 90
... Tcyc of the lowest speed transitioned between. Figure 50. RGMII Transmit Signal Timing Diagram Original i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev Description will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively. cyc 1 (continued) Min. Max. Unit 1 2 — 0.75 ns Freescale Semiconductor ...
Page 91
... HDMI Module Timing Parameters 4.11.7.1 Latencies and Timing Information Power-up time (time between TX_PWRON assertion and TX_READY assertion) for the HDMI 3D Tx PHY while operating with the slowest input reference clock supported (13.5 MHz) is 3.35 ms. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Electrical Characteristics 91 ...
Page 92
... The table below provides electrical characteristics for the HDMI 3D Tx PHY. The following three figures illustrate various definitions and measurement conditions specified in the table below. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev Figure 53. Driver Measuring Conditions Figure 54. Driver Definitions Figure 55. Source Termination Freescale Semiconductor ...
Page 93
... Hot plug detect time delay t 4.11.8 Switching Characteristics Table 63 describes switching characteristics for the HDMI 3D Tx PHY. various parameters specified in table. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 62. Electrical Characteristics Condition Operating conditions for HDMI - - TMDS drivers DC specifications For measurement conditions and definitions, see the first two figures above ...
Page 94
... All dynamic parameters related to the TMDS line drivers’ performance imply the use of assembly guidelines. Figure 57. Eye Diagram Mask Definition for HDMI Driver Signal Specification at TP1 i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev NOTE Figure 56. TMDS Clock Signal Definitions Figure 58. Intra-Pair Skew Definition Freescale Semiconductor ...
Page 95
... TMDSCLK high time CPH t TMDSCLK low time CPL — TMDSCLK jitter t Intra-pair (pulse) skew SK(p) i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Figure 59. Inter-Pair Skew Definition Table 63. Switching Characteristics Conditions TMDS Drivers Specifications — On TMDSCLKP/N outputs Ω See Figure 56. t ...
Page 96
... IC9 IC3 STOP START Standard Mode Fast Mode Min Max Min 10 — 2.5 4.0 — 0.6 4.0 — 0 3.45 0 4.0 — 0.6 4.7 — 1.3 4.7 — 0.6 Freescale Semiconductor START Unit Max µ — s µ — s µ — µ 0.9 s µ — s µ — s µ — ...
Page 97
... Related image processing and manipulation: sensor image signal processing, display processing, image conversions, and other related functions. • Synchronization and control capabilities, such as avoidance of tearing artifacts. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor 2 C Module Timing Parameters (continued) Standard Mode Min 250 4 ...
Page 98
... R/G/B[4] R/G/B[0] Y/C[0] R/G/B[5] R/G/B[1] Y/C[1] R/G/B[0] R/G/B[2] Y/C[2] R/G/B[1] R/G/B[3] Y/C[3] R/G/B[2] R/G/B[4] Y/C[4] R/G/B[3] R/G/B[5] Y/C[5] R/G/B[4] R/G/B[6] Y/C[6] R/G/B[5] R/G/B[7] Y/C[ RGB565 YCbCr YCbCr 16 bits 16 bits 16 bits 2 cycles 1 cycle 1 cycle — — 0 — — 0 — — C[0] — — C[1] B[0] C[0] C[2] B[1] C[1] C[3] B[2] C[2] C[4] B[3] C[3] C[5] B[4] C[4] C[6] G[0] C[5] C[7] G[1] C[6] 0 G[2] C[7] 0 G[3] Y[0] Y[0] G[4] Y[1] Y[1] G[5] Y[2] Y[2] R[0] Y[3] Y[3] R[1] Y[4] Y[4] R[2] Y[5] Y[5] R[3] Y[6] Y[6] R[4] Y[7] Y[7] Freescale Semiconductor 8 YCbCr 20 bits 1 cycle C[0] C[1] C[2] C[3] C[4] C[5] C[6] C[7] C[8] C[9] Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] Y[8] Y[9] ...
Page 99
... SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the SENSB_VSYNC timing repeats. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Electrical Characteristics 99 ...
Page 100
... SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 100 Section 4.11.10.2.2, “Gated Clock Figure n+1th frame invalid 1st byte is that of a typical sensor. Some other sensors may have a slightly Mode,”) 63). All incoming pixel clocks are 1st byte Freescale Semiconductor ...
Page 101
... Data and control holdup time 4.11.10.4 IPU Display Interface Signal Mapping The IPU supports a number of display output video formats. Interface Pins used during various supported video interface formats. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor IP2 IP3 Figure 64. Sensor Interface Timing Diagram Symbol ...
Page 102
... The restrictions are as follows: • There are maximal three continuous groups of bits that C[1] could be independently mapped to the external bus. C[2] Groups should not be overlapped. C[3] • The bit order is expressed in each of the bit groups, for C[4] example, B[0] = least significant blue pixel bit C[5] C[6] C[7] C[8] C[9] Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] Y[8] Y[9] — — Freescale Semiconductor ...
Page 103
... This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data during blanking intervals is not supported. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor LCD RGB/TV Signal Allocation (Example) 16-bit ...
Page 104
... When a DI decides to put a new asynchronous data in the bus, a new internal start (local start point) is generated. The signals generators calculate predefined UP and DOWN values to change pins states with half DI_CLK resolution. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 104 NOTE NOTE Freescale Semiconductor ...
Page 105
... VSYNC HSYNC LINE 1 HSYNC DRDY IPP_DISP_CLK IPP_DATA Figure 65. Interface Timing Diagram for TFT (Active Matrix) Panels i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor LINE 2 LINE 3 LINE Electrical Characteristics LINE n-1 LINE n ...
Page 106
... All parameters shown in the figure are programmable. IP13 VSYNC HSYNC DRDY IP11 Figure 67. TFT Panels Timing Diagram—Vertical Sync Pulse i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 106 IP8o IP8 D0 IP9o IP9 IP6 Start of frame IP14 IP12 IP7 IP5 Dn D1 IP10 End of frame IP15 Freescale Semiconductor ...
Page 107
... IP10 Horizontal blank interval 2 IP12 Screen height IP13 VSYNC width IP14 Vertical blank interval 1 IP15 Vertical blank interval 2 i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Figure 66 Symbol Value 1 Tdicp ( ) Display interface clock. Tdpcp DISP_CLK_PER_PIXEL Time of translation of one pixel to display, × ...
Page 108
... DRDY_OFFSET—offset of DRDY edges from a suitable local start point, when a corresponding data has been set on the × bus, in DI_CLK 2 (0.5 DI_CLK Resolution). The DRDY_OFFSET should be built by suitable DI’s counter. DISP_CLK_PERIOD for integer --------------------------------------------------- - DI_CLK_PERIOD for fractional DISP_CLK_PERIOD ---------------------------------------------------- DI_CLK_PERIOD Freescale Semiconductor Unit ...
Page 109
... The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be chip specific. 2 Display interface clock down time i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor ± Accuracy = T 0.62ns ...
Page 110
... GND and IO Supply Voltage Table 71. Electrical and Timing Information Test Conditions Transient voltage range is limited from -300 mV to 1600 mV ⎞ ⎠ Min Max 250 450 1.25 1.6 0.9 1.25 1.15 1.375 -50 50 -24 24 247 454 MIN TYP MAX Unit -50 — 1350 mV Freescale Semiconductor Units ...
Page 111
... Single-ended output OLP(0-11) impedance mismatch driving same level V Differential input high IDTH voltage threshold i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor VGNDSH(min -10 VGNDSH(max) + VOH(absmax) Lane module in LP Receive Mode -50 HS Line Drivers DC Specifications 80 Ω<= RL< = 125 Ω 140 80 Ω ...
Page 112
... Input high voltage IH V Input hysteresis HYST V Input low fault threshold ILF i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 112 LP Line Receiver DC Specifications Contention Line Receiver DC Specifications -70 mV 460 mV - 330 mV Ω 80 125 550 mV 920 200 450 mV Freescale Semiconductor ...
Page 113
... Ideal Differential High Speed Signals 0V (Differential Figure 70. Ideal Single-ended and Resulting Differential HS Signals i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Threshold Region V OHHS Max CMTX,MAX V CMTX,MIN Min OLHS Figure 69. D-PHY Signaling Levels ...
Page 114
... Ω 20 Ω OD (1) MIN TYP MAX 80 — 1000 40 — 500 2 — 25 — 50 — — 1 — — 1 — — 75 — 0.075 0.350 0.650 0.15 0.15 150 0.3UI 150 0.3UI 15 Freescale Semiconductor Unit Mbps MHz pk– rms ...
Page 115
... S R Equivalent wire bond series resistance S R Load resistance L 4.11.12.6 High-Speed Clock Timing CLKp CLKn i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 72. Electrical and Timing Information Test Conditions 80 Ω<= RL< = 125 Ω LP Line Drivers AC Specifications 15% to 85%, C < 30% to 85%, C < 15% to 85%, C < ...
Page 116
... Figure 75. Input Glitch Rejection of Low-Power Receivers i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 116 Reference Time T T SETUP HOLD 0.5UI + INST T SKEW 1 UI INST T CLKp Figure 73. Data to Clock Timing Definitions T TD Clock to Data Skew 2UI 2UI 2*T LPX 2*T LPX e SPIKE T MIN-RX Freescale Semiconductor ...
Page 117
... FLAG N-bits Frame READY Receiver has detected the start of the Frame Figure 78. Receiver Real-Time Data Flow READY Signal Timing i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Last bit of First bit of frame frame Receiver has captured and stored a complete Frame ...
Page 118
... PHY Frame 3. First bit received 4. Received frame stored start state C B: Wake-up state C: Active state (full operational) D PHY Frame 6. Receiver can no longer receive date 5. Transmitter has no more data to transmit D: Disable State(No communication ability) Complete N-bits Frame Complete N-bits Frame Freescale Semiconductor ...
Page 119
... This case shows that the DATA signal has slowed down more compared to the FLAG signal 2 This case shows that the FLAG signal has slowed down more compared to the DATA signal. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Complete N-bits Frame Table 73. DATA and FLAG Timing Description ...
Page 120
... PWM output pulse width high P2 PWM output pulse width low i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 120 Table 74 lists the PWM timing parameters. Figure 84. PWM Timing Table 74. PWM Output Timing Parameters Min Max Unit ipg_clk MHz ns ns Freescale Semiconductor ...
Page 121
... Data Inputs Data Outputs Data Outputs Data Outputs Figure 86. Boundary Scan (JTAG) Timing Diagram i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Figure 86 depicts the SJC boundary scan timing. SJ1 SJ2 VM VIH VIL Figure 85. Test Clock Input Timing Diagram SJ4 ...
Page 122
... Output Data Valid SJ11 SJ10 Output Data Valid SJ13 Figure 88. TRST Timing Diagram Table 75. JTAG Timing 1,2 Parameter VIH SJ9 All Frequencies Unit Min Max 0.001 22 MHz 45 — ns 22.5 — ns — — — ns — — — ns Freescale Semiconductor ...
Page 123
... SRCK high period SRCK low period Modulating Tx clock (STCLK) period STCLK high period STCLK low period i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 75. JTAG Timing (continued) 1,2 Parameter show SPDIF timing parameters for the Sony/Philips Digital Table 76. SPDIF Timing Parameters Symbol — ...
Page 124
... Table 77. AUDMUX Port Allocation Type and Access SSI 1 Internal SSI 2 Internal AUD3 External— AUD3 I/O AUD4 External— EIM or CSPI1 I/O through IOMUXC AUD5 External— EIM or SD1 I/O through IOMUXC AUD6 External— EIM or DISP2 through IOMUXC SSI 3 Internal NOTE M M Freescale Semiconductor ...
Page 125
... SS15 (Tx/Rx) Internal FS fall time SS16 (Tx) CK high to STXD valid from high impedance SS17 (Tx) CK high to STXD high/low SS18 (Tx) CK high to STXD high impedance i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 78 SS1 SS5 SS4 SS8 SS10 SS14 SS16 SS17 ...
Page 126
... For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 126 Parameter Synchronous Internal Clock Operation NOTE Min Max Unit 10.0 — ns 0.0 — ns Freescale Semiconductor ...
Page 127
... SS11 (Rx) CK high to FS (wl) high SS13 (Rx) CK high to FS (wl) low SS20 SRXD setup time before (Rx) CK low SS21 SRXD hold time after (Rx) CK low i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 79 SS1 SS5 SS4 SS9 SS11 SS20 SS51 ...
Page 128
... For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 128 Parameter NOTE Min Max Unit 15.04 — ns 6.0 — ns — 3.0 ns 6.0 — ns — 3.0 ns Freescale Semiconductor ...
Page 129
... SS31 (Tx) CK high to FS (wl) high SS33 (Tx) CK high to FS (wl) low SS37 (Tx) CK high to STXD valid from high impedance SS38 (Tx) CK high to STXD high/low i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 80 SS22 SS25 SS26 SS27 SS29 SS31 SS37 SS44 ...
Page 130
... For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 130 Parameter Synchronous External Clock Operation NOTE Min Max Unit — 15.0 ns 10.0 — ns 2.0 — ns — 6.0 ns Freescale Semiconductor ...
Page 131
... CK high to FS (wl) low SS35 (Tx/Rx) External FS rise time SS36 (Tx/Rx) External FS fall time SS40 SRXD setup time before (Rx) CK low SS41 SRXD hold time after (Rx) CK low i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 81 SS22 SS26 SS25 SS28 SS30 SS32 SS35 SS40 ...
Page 132
... DCE Mode Description Input RTS from DTE to DCE CTS from DCE to DTE Input DTR from DTE to DCE DSR from DCE to DTE DCD from DCE to DTE RING from DCE to DTE Serial data from DCE to DTE Input Serial data from DTE to DCE Freescale Semiconductor ...
Page 133
... The UART receiver can tolerate 1/( exceed 3/( baud_rate 2 : Baud rate frequency. The maximum baud rate the UART can support is ( ipg_perclk frequency)/16. F baud_rate i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor UA1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Symbol Min ...
Page 134
... ref_clk ref_clk Table 86 UA6 UA5 UA5 Bit 5 Bit 6 Bit 7 Possible Parity Bit Min Max 2 - 1/(16 1/F + 1/(16 x baud_rate baud_rate baud_rate baud_rate 1.41 μs (5/16) x (1/F baud_rate Freescale Semiconductor lists STOP BIT Unit — ) — lists STOP BIT Unit — ) — ...
Page 135
... Tstrobe strobe period Todelay data output delay time Tslew strobe/data rising/falling time i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor ) tolerance in each bit. But accumulation tolerance in one frame must not baud_rate NOTE Tstrobe Todelay Figure 99. USB HSIC Transmit Waveform Table 87. USB HSIC Transmit Parameters ...
Page 136
... Applications Processors for Consumer Products, Rev. 1 136 Tstrobe Thold Tsetup Figure 100. USB HSIC Receive Waveform Table 88. USB HSIC Receive Parameters Min Max Unit 4.166 4.167 ns 300 ps 365 ps 0.7 2 V/ns 1 Comment Measured at 50% point Measured at 50% point Averaged from 30% – 70% points Freescale Semiconductor ...
Page 137
... Fuse Map document and the System Boot chapter in i.MX 6Solo/6DualLite Reference Manual (IMX6SDLRM). Table 89. Fuses and Associated Pins Used for Boot Pin Direction at Reset BOOT_MODE1 BOOT_MODE0 i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor eFuse Name Input N/A Input N/A Boot Mode Configuration Details ...
Page 138
... Input BOOT_CFG4[7] Details Boot Options, Pin value overrides fuse settings for BT_FUSE_SEL = ‘0’. Signal Configuration as Fuse Override Input at Power Up. These are special I/O lines that control the boot up configuration during product development. In production, the boot configuration can be controlled by fuses. Freescale Semiconductor ...
Page 139
... EIM_D18, EIM_D17 USB USB-OTG USB_OTG_DP PHY USB_OTG_DN USB_OTG_VBUS i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 90. Interface Allocation During Boot Allocated Pads During Boot Boot Mode Configuration Comment Used for NOR, OneNAND boot Only CS0 is supported 8 bit Only CS0 is supported ...
Page 140
... This section includes the contact assignment information and mechanical package drawing. 6.1 21x21 mm Package Information 6.1.1 Case 2240 mm, 0.8 mm Pitch Ball Matrix Figure 101 shows the top, bottom, and side views of the 21×21 mm BGA package. i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 140 Freescale Semiconductor ...
Page 141
... Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 141 ...
Page 142
... Package Information and Contact Assignments Figure 101 BGA, Case 2240 Package Top, Bottom, and Side Views i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 142 Freescale Semiconductor ...
Page 143
... G18 NVCC_SD1 G16 NVCC_SD2 G17 NVCC_SD3 G14 i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Ball(s) Position(s) Remark Supply of the camera sensor interface Supply of the DDR interface Supply of the EIM interface Supply of the ENET interface ...
Page 144
... Primary supply for SoC and PU regulators Secondary supply for the 3 V Domain (internal regulator output—requires capacitor if internal regulator is used) Primary supply for the 3 V regulator Primary supply for the 3 V regulator Analog Ground(Ground reference for the Hot Plug Detect signal) Freescale Semiconductor ...
Page 145
... CSI0_DAT17 L3 NVCC_CSI CSI0_DAT18 M6 NVCC_CSI CSI0_DAT19 L6 NVCC_CSI CSI0_DAT4 N1 NVCC_CSI CSI0_DAT5 P2 NVCC_CSI i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Ball(s) Position(s) Ball Default Type Mode Default Function (Reset Mode) GPIO ALT0 src.BOOT_MODE[0] GPIO ALT0 src.BOOT_MODE[1] ANALOG ...
Page 146
... Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Freescale Semiconductor ...
Page 147
... NVCC_DRAM DRAM_D0 AD2 NVCC_DRAM DRAM_D1 AE2 NVCC_DRAM DRAM_D10 AA6 NVCC_DRAM DRAM_D11 AE7 NVCC_DRAM i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 1 Out of Reset Condition Ball Default Type Mode Default Function (Reset Mode) GPIO ALT5 gpio4.GPIO[24] ...
Page 148
... Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Freescale Semiconductor ...
Page 149
... NVCC_DRAM DRAM_D63 W25 NVCC_DRAM DRAM_D7 AE4 NVCC_DRAM DRAM_D8 AD5 NVCC_DRAM DRAM_D9 AE5 NVCC_DRAM i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 1 (continued) Out of Reset Condition Ball Default Type Mode Default Function (Reset Mode) DDR ALT0 mmdc ...
Page 150
... Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Low Low Output Low - - Output Low - - Output Low Output Low Input Hi Input Hi Input Hi Input Hi Input Hi-Z Freescale Semiconductor ...
Page 151
... NVCC_EIM EIM_CS1 J23 NVCC_EIM EIM_D16 C25 NVCC_EIM EIM_D17 F21 NVCC_EIM EIM_D18 D24 NVCC_EIM i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 1 Out of Reset Condition Ball Default Type Mode Default Function (Reset Mode) DRAM_SDQS4_B DDRCLK ALT0 mmdc ...
Page 152
... Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Output High Freescale Semiconductor ...
Page 153
... GPIO_4 R6 NVCC_GPIO GPIO_5 R4 NVCC_GPIO GPIO_6 T3 NVCC_GPIO GPIO_7 R3 NVCC_GPIO GPIO_8 R5 NVCC_GPIO i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 1 Out of Reset Condition Ball Default Type Mode Default Function (Reset Mode) GPIO ALT0 weim.WEIM_EB[1] GPIO ALT5 gpio2.GPIO[30] ...
Page 154
... Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-down Input Keeper Input Keeper Freescale Semiconductor ...
Page 155
... NVCC_NANDF NANDF_CS2 A17 NVCC_NANDF NANDF_CS3 D16 NVCC_NANDF NANDF_D0 A18 NVCC_NANDF NANDF_D1 C17 NVCC_NANDF i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 1 Out of Reset Condition Ball Default Type Mode Default Function (Reset Mode) ALT0 ldb.LVDS0_TX1 ALT0 ldb ...
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... Input 100 kΩ pull-up Input 100 kΩ pull-down Input 100 kΩ pull-down Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-down Input 100 kΩ pull-down Freescale Semiconductor ...
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... NVCC_NANDF SD4_CMD B17 NVCC_NANDF SD4_DAT0 D18 NVCC_NANDF SD4_DAT1 B19 NVCC_NANDF SD4_DAT2 F17 NVCC_NANDF i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 1 Out of Reset Condition Ball Default Type Mode Default Function (Reset Mode) GPIO ALT5 gpio1.GPIO[20] ...
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... GPIO ALT0 snvs_lp_wrapper.SNVS_ TD1 GPIO ALT0 tcu.TEST_MODE (continued) 2 Input/ Outpu Value t Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-down Input 100 kΩ pull-down Freescale Semiconductor ...
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... Pitch Ball Map Table 93 shows the mm, 0.8 mm pitch ball map for the i.MX 6Solo. Table 93 mm, 0.8 mm Pitch Ball Map i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 159 ...
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... Package Information and Contact Assignments Table 93 mm, 0.8 mm Pitch Ball Map (continued) i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 160 Freescale Semiconductor ...
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... Table 93 mm, 0.8 mm Pitch Ball Map (continued) i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 161 ...
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... Package Information and Contact Assignments Table 93 mm, 0.8 mm Pitch Ball Map (continued) Table 94 shows the mm, 0.8 mm pitch ball map for the i.MX 6DualLite. Table 94 mm, 0.8 mm Pitch Ball Map i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 162 Freescale Semiconductor ...
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... Table 94 mm, 0.8 mm Pitch Ball Map (continued) i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 163 ...
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... Package Information and Contact Assignments Table 94 mm, 0.8 mm Pitch Ball Map (continued) i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 164 Freescale Semiconductor ...
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... Table 94 mm, 0.8 mm Pitch Ball Map (continued) i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 165 ...
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... VDD_SNVS_IN parameter. 24. 25, removed VDD_CACHE_CAP load. 27. 30. 31. 36, added 100 kΩ as ESR parameter max value. 40. 49, Multiplexed Address/Data mode, 16 Bit 76, updated CS5 and CS6 min values. 89. 89. 114, updated ΔV 120. 120. 4. max value. CMTX(LF) Freescale Semiconductor ...
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... Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. ARM is the registered trademark of ARM Limited. ARM Cortex™- trademark of ARM Limited. © ...