BR24L02F-WE2 Rohm Semiconductor, BR24L02F-WE2 Datasheet - Page 10

• Manufacturer Part Number: BR24L02F-WE2
• Description: IC EEPROM 2KBIT 400KHZ 8SOP
• Manufacturer: Rohm Semiconductor

Specifications of BR24L02F-WE2

• Memory Size: 2K (256 x 8)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOP
• Clock Frequency: 400kHz
• Supply Voltage Range: 1.8V To 5.5V
• Memory Case Style: SOP
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Organization: 256 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.1 MHz
• Access Time: 3500 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 1.8 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: BR24L02F-WE2TR

Software reset
Acknowledge polling
During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic write execution
after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back "L", then it means end of write action,
while if it sends back "H", it means now in writing. By use of acknowledge polling, next command can be executed without waiting for
tWR = 5ms.
When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if ACK signal
sends back "L", then execute word address input and data output and so forth.
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset has several
kinds, and 3 kinds of them are shown in the figure below. (Refer to Fig. 48 (a), Fig. 48 (b) and Fig. 48 (c).) In dummy clock input area,
release the SDA bus ("H" by pull up). In dummy clock area, ACK output and read data "0" (both "L" level) may be output from EEPROM,
therefore, if "H" is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power
source or influence upon devices.
S
T
A
R
T
S
A
R
T
T
First write command
* Start normal command from START input.
SCL
SDA
SCL
SDA
Slave address
SCL
SDA
Write command
t
WR
Fig.49 Case to continuously write by acknowledge polling
Fig.48-(b) The case of START + 9 dummy clocks + START + command input
Fig.48-(a) The case of dummy clock + START + START + command input
A
C
K
H
Start
1
1
S
T
O
P
Dummy clock × 14
2
Fig.48-(c) START
1
2
R
S
T
A
T
R
S
T
A
T
Dummy clock × 9
2
3
Slave address
10/16
Slave address
Start × 9
13
×
9 + command input
A
C
K
L
14
8
7
A
C
K
H
Second write command
Word address
Start × 2
9
t
8
WR
After completion of internal
write, ACK = LOW is sent
back, so input next word
address and data in
succession.
During internal write,
ACK = HIGH is sent back.
Start
S
T
A
R
T
9
A
C
K
L
Slave address
Data
Normal command
Normal command
Normal command
Normal command
Normal command
Normal command
A
C
K
H
A
C
K
L
O
S
T
P