BR24L02F-WE2 Rohm Semiconductor, BR24L02F-WE2 Datasheet - Page 6

• Manufacturer Part Number: BR24L02F-WE2
• Description: IC EEPROM 2KBIT 400KHZ 8SOP
• Manufacturer: Rohm Semiconductor

Specifications of BR24L02F-WE2

• Memory Size: 2K (256 x 8)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOP
• Clock Frequency: 400kHz
• Supply Voltage Range: 1.8V To 5.5V
• Memory Case Style: SOP
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Organization: 256 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.1 MHz
• Access Time: 3500 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 1.8 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: BR24L02F-WE2TR

I2C BUS communication
I
I
acknowledge is always required after each byte.
I
clock (SCL).
Among devices, there are "master" that generates clock and control communication start and end, and "slave" that is controlled
by addresses peculiar to devices.
EEPROM becomes "slave". And the device that outputs data to bus during data communication is called "transmitter", and the
device that receives data is called "receiver".
Start condition (start bit recognition)
Stop condition (stop bit recognition)
Device addressing
2
2
2
C BUS data communication
C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and
C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and serial
Acknowledge (ACK) signal
Before executing each command, start condition (start bit) where SDA goes from "HIGH" down to "LOW" when SCL is "HIGH" is
This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is satisfied, any
Each command can be ended by SDA rising from "LOW" to "HIGH" when stop condition (stop bit), namely, SCL is "HIGH"
Output slave address after start condition from master.
The significant 4 bits of slave address are used for recognizing a device type.
Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same bus according
The most insignificant bit (R/W --- READ/WRITE) of slave address is used for designating write or read action, and is as shown
necessary.
command is executed.
The device code of this IC is fixed to "1010".
to the number of device addresses.
below.
Note) Up to 4 units of BR24L04-W, up to 2 units of BR24L08-W, and one unit of
PS, P0 ~ P2 are page select bits.
This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master and
The device (this IC at slave address input of write command, read command, and µ-COM at data output of read command) at the
This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) "LOW".
Each write action outputs acknowledge signal (ACK signal) "LOW", at receiving 8bit data (word address and write data).
Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) "LOW".
When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side, this IC continues
slave, the device (µ-COM at slave address input of write command, read command, and this IC at data output of read command)
at the transmitter (sending) side releases the bus after output of 8bit data.
receiver (receiving) side sets SDA "LOW" during 9 clock cycles, and outputs acknowledge signal (ACK signal) showing that it has
received the 8bit data.
data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes stop condition
(stop bit), and ends read action.
And this IC gets in standby status.
BR24L01A-W
BR24L02-W
BR24L04-W
BR24L08-W
BR24L16-W
BR24L32-W
BR24L64-W
Setting R/W to 0 --- write (setting 0 to word address setting of random read)
Setting R/W to 1 --- read
BR24L16-W can be connected.
Device address is set by "H" and "L" of each pin of A0, A1, and A2.
Type
1
1
1
1
1
1
1
0
0
0
0
0
0
0
SDA
SCL
1
1
1
1
1
1
1
condition
START
S
Slave address
0
0
0
0
0
0
0
ADDRESS
1-7
P2
A2
A2
A2
A2
A2
A2
R/W
8
ACK
9
P1 P 0 R/
P1 P 0 R/
A1 A0 R/
A1 A0 R/
A1
A1 A0 R/
A1 A0 R/
Fig.35 Data transfer timing
6/16
P S
1-7
DATA
R/
8
W
W
W
W
W
W
W
ACK
9
of connected buses
Maximum number
1-7
DATA
8
8
4
2
1
8
8
8
ACK
9
condition
STOP
P
GND
A0
A1
A2
1
2
3
4
BR24L01A-W
BR24L02-W
BR24L04-W
BR24L08-W
BR24L16-W
BR24L32-W
BR24L64-W
8
7
6
5
SDA
SCL
V
WP
CC