BR24L02F-WE2 Rohm Semiconductor, BR24L02F-WE2 Datasheet - Page 9

• Manufacturer Part Number: BR24L02F-WE2
• Description: IC EEPROM 2KBIT 400KHZ 8SOP
• Manufacturer: Rohm Semiconductor

Specifications of BR24L02F-WE2

• Memory Size: 2K (256 x 8)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOP
• Clock Frequency: 400kHz
• Supply Voltage Range: 1.8V To 5.5V
• Memory Case Style: SOP
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Organization: 256 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.1 MHz
• Access Time: 3500 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 1.8 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: BR24L02F-WE2TR

Command
SDA
LINE
LINE
SDA
LINE
SDA
SDA
LINE
S
T
A
R
T
1
Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when to
verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be read in
succession.
In random read cycle, data of designated word address can be read.
When the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle),
data of incremented last read address (n-th) address, i.e., data of the (n+1)-th address is output.
When ACK signal "LOW" after D0 is detected, and stop condition is not sent from the master (µ-COM) side, the next address data can
be read in succession.
Read cycle is ended by stop condition where "H" is input to ACK signal after D0 and SDA signal is started at SCL signal "H".
When "H" is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input "H" to ACK
signal after D0, and to start SDA at SCL signal "H".
Sequential read is ended by stop condition where "H" is input to ACK signal after arbitrary D0 and SDA is started at SCL signal "H".
0
S
A
R
S
A
R
T
T
T
T
S
T
A
R
T
ADDRESS
1
1
1
SLAVE
1
0 A2
Note)
0
0
ADDRESS
ADDRESS
0
1
1
Note)
SLAVE
SLAVE
Note)
ADDRESS
A1 A0
0 A2A1A0
0 A2A1A0
1
SLAVE
0 A2 A1 A0
Note)
W
R
E
A
D
R
/
Fig.46 Sequential read cycle (in the case of current read cycle)
Fig.43 Random read cycle (BR24L01A/02/04/08/16-W)
Fig.45 Current read cycle
Fig.44 Random read cycle (BR24L32/64-W)
A
C
K
W
W
R
R
T
E
I
/
W
R
W
R
T
E
D7
/
I
A
C
K
A
C
K
WA
7
*1
* * *
W
R
E
A
D
R
/
DATA(n)
ADDRESS(n)
ADDRESS(n)
C
A
K
1st WORD
WORD
D7
WA
12
*1
WA
11
D0
WA
DATA
0
A
C
K
A
C
K
C
A
K
S
T
A
R
T
1
0
ADDRESS(n)
2nd WORD
ADDRESS
1
D0
SLAVE
0
A
C
K
A2A1A0
O
S
T
P
Note)
WA
0
W
R
E
A
D
R
/
A
C
K
A
C
K
A
C
K
R
S
T
A
T
D7
D7
Fig.47 Difference of slave address of each type
1
0
DATA(n+x)
DATA(n)
ADDRESS
1
1 0 1 0
SLAVE
0
A2A1A0
D0
D0
W
A
C
K
R
E
A
D
R
/
O
A
C
K
A
C
K
S
T
P
D7
S
T
O
P
9/16
A2A1A0
DATA(n)
* 1 * 2 * 3
D0
C
A
K
S
O
P
T
It is necessary to input "H"
to the last ACK.
It is necessary to input "H"
to the last ACK.
It is necessary to input "H"
to the last ACK.
*1 In BR24L16-W, A2 becomes P2.
*2 In BR24L08-W, BR24L16-W, A1 becomes P1.
*3 In BR24L04-W, A0 becomes PS, and in BR24L08-W
and BR24L16-W, A0 becomes P0.
*1
*1
As for WA7, BR24L01A-W become Don't care.
As for WA12, BR24L32-W become Don't care.