BR24L04FVM-WTR Rohm Semiconductor, BR24L04FVM-WTR Datasheet - Page 11

• Manufacturer Part Number: BR24L04FVM-WTR
• Description: IC EEPROM 4KBIT 400KHZ 8MSOP
• Manufacturer: Rohm Semiconductor

Specifications of BR24L04FVM-WTR

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Organization: 512 x 8
• Interface Type: 2-Wire
• Maximum Clock Frequency: 0.4 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WP valid timing (write cancel)
Command cancel by start condition and stop condition
WP is usually fixed to "H" or "L", but when WP is used to cancel write cycle and so forth, pay attention to the following WP valid timing.
During write cycle execution, in cancel valid area, by setting WP = "H", write cycle can be cancelled. In both byte write cycle and page
write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of data (in page write cycle, the first byte
data) is cancel invalid area.
WP input in this area becomes Don't care. Set the setup time to rise of D0 taken SCL 100ns or more. The area from the rise of SCL to
take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP = "H" during tWR, write is ended
forcibly, data of address under access is not guaranteed, therefore, write it once again. (Refer to Fig. 50.) After execution of forced end by
WP, standby status gets in, so there is no need to wait for tWR (5ms at maximum).
During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Refer to Fig. 51.)
However, in ACK output area and during data read, SDA bus may output "L", and in this case, start condition and stop condition cannot
be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by start, stop condition, during
random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to
carry out current read cycle in succession. When to carry out read cycle in succession, carry out random read cycle.
SDA
WP
S
T
A
R
T
address
Slave
SCL
SDA
SCL
SDA
A
C
K
L
Rise of D0 taken clock
address
Word
WP cancel invalid area
Enlarged view
Fig.51 Case of cancel by start, stop condition during slave address input
D1
C
A
K
L
D7
D0
1
D6
ACK
D5
Fig.50 WP valid timing
D4
0
D3
11/16
D2
1
D1
D0
A
C
K
L
0
WP cancel valid area
Data is not written.
Data
Start condition
SDA
SCL
D0
Enlarged view
A
C
K
L
O
S
T
P
ACK
Stop condition
Data not guaranteed
Write forced end
Rise of SDA
tWR