BR24L04FVM-WTR Rohm Semiconductor, BR24L04FVM-WTR Datasheet - Page 15

• Manufacturer Part Number: BR24L04FVM-WTR
• Description: IC EEPROM 4KBIT 400KHZ 8MSOP
• Manufacturer: Rohm Semiconductor

Specifications of BR24L04FVM-WTR

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Organization: 512 x 8
• Interface Type: 2-Wire
• Maximum Clock Frequency: 0.4 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes on power ON
Low voltage malfunction prevention function
Vcc noise countermeasures
Cautions on use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In
(3) Absolute maximum ratings
(4) GND electric potential
(5) Thermal design
(6) Terminal to terminal shortcircuit and wrong packaging
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
3. Set SDA and SCL so as not to become "Hi-Z".
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset, and
malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action, observe the
following conditions at power on.
1. Set SDA = "H" and SCL = "L" or "H".
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. = 1.2V) or below, it prevent data
rewrite.
Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a
by pass capacitor (0.1µF) between IC Vcc and GND. At that moment, attach it as close to IC as possible.
And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static
characteristics and transition characteristics and fluctuations of external parts and our LSI.
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be
destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute
maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum
ratings should not be impressed to LSI.
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal.
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in
the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be
destructed.
a) In the case when the above condition 1 cannot be observed. When SDA becomes "L" at power on.
b) In the case when the above condition 2 cannot be observed.
c) In the case when the above conditions 1 and 2 cannot be observed.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
→Control SCL and SDA as shown below, to make SCL and SDA, "H" and "H".
→After power source becomes stable, execute software reset (P10).
→Carry out a), and then carry out b).
V
0
CC
After Vcc becomes stable
Vcc
SCL
SDA
Fig.61 When SCL = "H" and SDA = "L"
t
OFF
t
DH
t
R
tLOW
tSU:DAT
Fig.60 Rise waveform diagram
Vbot
15/16
Recommended conditions of t
100ms or below
10ms or below
After Vcc becomes stable
t
Fig.62 When SCL = "H" and SDA = "L"
R
10ms or higher
10ms or higher
t
OFF
R
tSU:DAT
, t
0.3V or below
0.2V or below
OFF
, Vbot
Vbot